\\Following is the Verilog code for a 4-bit unsigned Up counter with asynchronous clear. \\Number of bits can be changed to any number module cntr4bit(en,clk,clr,q); parameter n = 4; input en,clk,clr; output [n-1:0] q; reg [n-1:0] q; always @ (posedge clk) begin if (clr) q <= 0; else if (en) q <= q + 1 ; end endmodule