Student Name |
Dept. |
Deg. |
Thesis Title |
Defense
Date |
Role |
Syed
Zafar Shazli |
COE |
Msc |
Experimenting with Iterative Heuristics
for State Justification in Sequential ATPG. |
Apr. 2001 |
Supervisor |
Esam
Khan |
COE |
Msc |
A Two-Dimensional
Geometric-Primitives-Based Compression Scheme for
Testing Systems-on-a-Chip. |
May 2001 |
Supervisor |
Mahmood
Minhas |
COE |
Msc |
Iterative Algorithms for Timing and Low
Power Driven VLSI Standard Cell Placement. |
Apr.
2001 |
Committee Member |
Ali
Al-Suwaiyan |
COE |
Msc |
An Efficient Test Vector Relaxation
Technique for Combinational Circuits. |
|
Supervisor |
Khaled
Al-Utaibi |
COE |
Msc |
An
Efficient Test Relaxation Technique for Sequential Circuits. |
|
Supervisor |
Raslan
Al-Abaji |
COE |
Msc |
Evolutionary
Techniques for Multi-Objective VLSI Netlist Partitioning. |
April 2002 |
Co-Supervisor |
Yahya Osias |
COE |
Msc |
Efficient Test Compaction Techniques for Combinational & Sequential Circuits(Defense) | Oct. 2002 |
Supervisor |
Faisal Nawaz Khan | COE | Msc | FSM State-Assignment for Area, Power and Testability using Non-Deterministic Evolutionary Heuristics | May 2005(Defended) |
Supervisor |
Syed Saqib Khursheed | COE | Msc | Test Set Compaction for Sequential Circuits Based on Test Relaxation | Dec. 2004(Defended) |
Supervisor |
Mustafa Imran Ali | COE | Msc | An Efficient Relaxation-based Test Width Compression Technique for Multiple Scan Chain Testing | Sep. 2006(Defended) |
Supervisor |
Khawar Khan | COE | Msc | Parallelization of Stochastic Evolution for Cell Placement | June 2006(Defended) |
Committee Member |
Umair Farooq Siddiqi | COE | Msc | Parallel Algorithms for Look-Up Table (LUT) Inverse Halftoning | May 2007 (Defended) |
Committee Member |
Esa Al-Ghonaim | COE | PhD | LDPC Codes Design and Decoder Implementation | March 2008 (Expected) |
Supervisor |