Experiment 3. Digital Circuit Prototyping Using FPGAs

A project is a collection of all the files needed to create and download a design to the FPGA device. When creating a new project, usually you need to specify the project name, the location of its files on the hard drive, the type of input files (also called source files), and the target FPGA device that this design is created for.

To specify a digital design in your project, you add a source file to it. The most commonly used source formats are:

Verilog and VHDL are standard hardware description languages that are used to specify hardware design. We will explore using Verilog to specify designs in later experiments.

In this experiment, we will use schematic source files.

When using schematic design entry, the schematic editor provides a library of symbols. A symbol represents a circuit component, such as a logic gate. The library is a collection of ready-made design components. For example, you will find a symbol for the AND gate, and a symbol for the OR gate in the symbol library.

When creating a design, you must specify the inputs and the outputs of your design, so that you can connect them to the outside world. By specifying them in your schematic, you instruct the design software to make them available outside the FPGA, by connecting them later to pins of the FPGA chip.

To specify the input and output pins, use input and output markers in your schematic. Name your inputs and outputs appropriately to be able to identify them later.

Finally, you need to connect, or wire, all the components in your schematic design.

Simulation allows for testing the design and verifying its functionality without having to use the FPGA hardware. Instead, you use simulation software, or a simulator.

To simulate the design, you need to specify values for all inputs, run the simulator, and observe the output values and compare them to the expected output to determine if the circuit is working properly.

See the Simulation of a Half Adder Circuit figure for an example simulation. The Implementing a Half Adder section explains what the simulated circuit does.

In order to control the inputs and observe the outputs when your design is downloaded to the FGPA board, you need to configure the input signals of your design to be connected to some input peripherals on the FPGA board, and to configure your output signals to be connected to some output peripherals on the FPGA board.

Proper pin assignment requires that you carefully choose the input and output pins of your FPGA chip. You can lookup which FPGA chip pins are connected to which board peripherals by consulting the boards' user manual.

The synthesis and implementation phases collectively refer to a number of more specific steps. The first step accepts your design specification as input (schematic, Verilog, or VHDL), and the last step produces the FPGA configuration bitstream that implements your input design on the target FPGA.

These specific steps include transforming your input design to netlists, mapping the design to FPGA resources, placing the required resources on specific FGPA resources, and routing signals through FPGA interconnect resources.

More generally, this step combines all the available information, including your design, information about the target device, and any other additional constraints, to generate the configuration bitstream of the design.

Depending on the size of your design, and the size of the target FPGA device, this step can take anywhere from a fraction of a minute to several hours.

The Timing Report Table figure shows an example timing report, which lists estimates of how long it will take signals to propagate through your design when it is placed on the FPGA and the signals are routed through.

Timing reports allow you to verify whether your design can meet specific timing requirements.

Lastly, you configure the FPGA device by downloading the design configuration file (bitstream), which was generated at the end of the synthesize and implement step - you download it to the FPGA device.

To download the configuration file, you use the programmer tool of the design software suite. The programmer software can detect the FPGA device when it is connected to the development PC, typically using a USB cable.

Once the design is downloaded to the FPGA device successfully, you will be able to verify your design of the circuit by controlling the configured inputs and observing the outputs.

The Simulation of a Half Adder Circuit figure shows the behavior of the half-adder circuit, as obtained from a simulator. The figure shows the two inputs (A and B) and the two outputs (S and C). It also shows how the input values are changing over time, and how the outputs are responding to these changes.

To implement a half adder on an FPGA, the design must be created first. One way to create the design is using a schematic drawing, as explained in the Create Your Design section.

Then, the inputs of your half adder circuit, A and B, should be connected to two of the input pins of the FPGA chip that are already connected to switches on the board. Likewise, the outputs of your circuit, S and C should be connected to two output pins of the FPGA chip that are already connected to LEDs on the board.

This will allow you to manually test the circuit on the board by manipulating the connected switches and observing the connected LEDs.