ࡱ> (x/ / 0DArial Newmantt{ 0DComic Sans MSntt{ 0B DWingdings MSntt{ 00DTimes New Romantt{ 0@DCourier Newmantt{ 01PDSymbol Newmantt{ 0@ .  @n?" dd@  @@`` H@# w F jR -r[3|&+-G(!4--PPw4vQ7r "f     8-/!.R?_)   4(3 mJ v-   )p 60>!.+/ N] 7"f5 04vD6mC@0d:(W   +xK7 $ %"!L1O 6C#"L <6@Ek7}(`:\3Q4'$#("**'!/!,,][j~D;dAEef8[mzD Krhh.W ' \ =,W=Y.)  `c8   t   '%:S]a!?#=$%!&H'{(M)*+M,-.1%5:;<=>?@ABCD#E0FGDJKMN# 0AA ffff@f8w8 ʚ;3 ;ʚ;g4dddd  0Pppp@ <4dddd@w 0tz <4BdBd@x 0t80___PPT10 ZZ?  %O  =gXSingle Cycle Processor Design ,COE 308 Computer Architecture Prof. Muhamed Mudawar Computer Engineering Department King Fahd University of Petroleum and MineralsB4Z 0Zd/Z ,O'Presentation OutlineDesigning a Processor: Step-by-Step Datapath Components and Clocking Assembling an Adequate Datapath Controlling the Execution of Instructions The Main Controller and ALU Controller Drawback of the single-cycle processor design d$The Performance Perspective)Recall, performance is determined by: Instruction count Clock cycles per instruction (CPI) Clock cycle time Processor design will affect Clock cycles per instruction Clock cycle time Single cycle datapath and control design: Advantage: One clock cycle per instruction Disadvantage: long cycle time& <F < <. <* <I <&F.*I #Designing a Processor: Step-by-StepAnalyze instruction set => datapath requirements The meaning of each instruction is given by the register transfers Datapath must include storage elements for ISA registers Datapath must support each register transfer Select datapath components and clocking methodology Assemble datapath meeting the requirements Analyze implementation of each instruction Determine the setting of control signals for register transfer Assemble the control logic1 F F F? F F0f 4  "Review of MIPS Instruction FormatsAll instructions are 32-bit wide Three instruction formats: R-type, I-type, and J-type Op6: 6-bit opcode of the instruction Rs5, Rt5, Rd5: 5-bit source and destination register numbers sa5: 5-bit shift amount used by shift instructions funct6: 6-bit function field for R-type instructions immediate16: 16-bit immediate value or address offset immediate26: 26-bit target address of the jump instruction8[ ;   $2584/MIPS Subset of InstructionsOnly a subset of the MIPS instructions are considered ALU instructions (R-type): add, sub, and, or, xor, slt Immediate instructions (I-type): addi, slti, andi, ori, xori Load and Store (I-type): lw, sw Branch (I-type): beq, bne Jump (J-type): j This subset does not include all the integer instructions But sufficient to illustrate design of datapath and control Concepts used to implement the MIPS subset are used to construct a broad spectrum of computers60n20n20n26! d"Details of the MIPS SubsetRegister Transfer Level (RTL)RTL is a description of data flow between registers RTL gives a meaning to the instructions All instructions are fetched from memory at address PC Instruction RTL Description ADD Reg(Rd) ! Reg(Rs) + Reg(Rt); PC ! PC + 4 SUB Reg(Rd) ! Reg(Rs)  Reg(Rt); PC ! PC + 4 ORI Reg(Rt) ! Reg(Rs) | zero_ext(Im16); PC ! PC + 4 LW Reg(Rt) ! MEM[Reg(Rs) + sign_ext(Im16)]; PC ! PC + 4 SW MEM[Reg(Rs) + sign_ext(Im16)] ! Reg(Rt); PC ! PC + 4 BEQ if (Reg(Rs) == Reg(Rt)) PC ! PC + 4 + 4 sign_extend(Im16) else PC ! PC + 4 2K 2; @L++388T% & >"Instructions are Executed in Steps,R-type Fetch instruction: Instruction ! MEM[PC] Fetch operands: data1 ! Reg(Rs), data2 ! Reg(Rt) Execute operation: ALU_result ! func(data1, data2) Write ALU result: Reg(Rd) ! ALU_result Next PC address: PC ! PC + 4 I-type Fetch instruction: Instruction ! MEM[PC] Fetch operands: data1 ! Reg(Rs), data2 ! Extend(imm16) Execute operation: ALU_result ! op(data1, data2) Write ALU result: Reg(Rt) ! ALU_result Next PC address: PC ! PC + 4 BEQ Fetch instruction: Instruction ! MEM[PC] Fetch operands: data1 ! Reg(Rs), data2 ! Reg(Rt) Equality: zero ! subtract(data1, data2) Branch: if (zero) PC ! PC + 4 + 4sign_ext(imm16) else PC ! PC + 400n0n0n0n-n0n!  ' !  >J  * j. ( g u<Instruction Execution  cont dLW Fetch instruction: Instruction ! MEM[PC] Fetch base register: base ! Reg(Rs) Calculate address: address ! base + sign_extend(imm16) Read memory: data ! MEM[address] Write register Rt: Reg(Rt) ! data Next PC address: PC ! PC + 4 SW Fetch instruction: Instruction ! MEM[PC] Fetch registers: base ! Reg(Rs), data ! Reg(Rt) Calculate address: address ! base + sign_extend(imm16) Write memory: MEM[address] ! data Next PC address: PC ! PC + 4 Jump Fetch instruction: Instruction ! MEM[PC] Target PC address: target ! PC[31:28] , Imm26 ,  00 Jump: PC ! target,0n0n,0nP0n.0nPL0n$ $ # JQ n K #Requirements of the Instruction SetrMemory Instruction memory where instructions are stored Data memory where data is stored Registers 32 32-bit general purpose registers, R0 is always zero Read source register Rs Read source register Rt Write destination register Rt or Rd Program counter PC register and Adder to increment PC Sign and Zero extender for immediate constant ALU for executing instructionsR   %h >( Next . . .Designing a Processor: Step-by-Step Datapath Components and Clocking Assembling an Adequate Datapath Controlling the Execution of Instructions The Main Controller and ALU Controller Drawback of the single-cycle processor design( d$!Components of the DatapathCombinational Elements ALU, Adder Immediate extender Multiplexers Storage Elements Instruction memory Data memory PC register Register file Clocking methodology Timing of reads and writes -+ - -9 - - -+9 Register ElementRegister Similar to the D-type Flip-Flop n-bit input and output Write Enable: Enable / disable writing of register Negated (0): Data_Out will not change Asserted (1): Data_Out will become Data_In after clock edge Edge triggered Clocking Register output is modified at clock edge F  F% F F F* F %w  > TMIPS Register File#Register File consists of 32 32-bit registers BusA and BusB: 32-bit output busses for reading 2 registers BusW: 32-bit input bus for writing a register when RegWrite is 1 Two registers read and one written in a cycle Registers are selected by: RA selects register to be read on BusA RB selects register to be read on BusB RW selects the register to be written Clock input The clock input is used ONLY during write operation During read, register file behaves as a combinational logic block RA or RB valid => BusA or BusB valid after access time0 # # #u # #v #7 #0//4       3    + 0//q#Details of the Register File Tri-State BuffersAllow multiple sources to drive a single bus Two Inputs: Data signal (data_in) Output enable One Output (data_out): If (Enable) Data_out = Data_in else Data_out = High Impedance state (output is disconnected) Tri-state buffers can be used to build multiplexors 9$? 9$? tFY Building a Multifunction ALU Instruction and Data MemoriesInstruction memory needs only provide read access Because datapath does not write instructions Behaves as combinational logic for read Address selects Instruction after access time Data Memory is used for load and store MemRead: enables output on Data_out Address selects the word to put on Data_out MemWrite: enables writing of Data_in Address selects the memory word to be written The Clock synchronizes the write operation Separate instruction and data memories Later, we will replace them with caches~2 # #' #$ #, #% #Y #' #( #2U  '       +"'!b$Clocking MethodologyClocks are needed in a sequential logic to decide when a state element (register) should be updated To ensure correctness, a clocking methodology defines when data can be written and read( 2~+Determining the Clock CycleWith edge-triggered clocking, the clock cycle must be long enough to accommodate the path from one register through the combinational logic to another register  Clock SkewBClock skew arises because the clock signal uses different paths with slightly different delays to reach state elements Clock skew is the difference in absolute time between when two storage elements see a clock edge With a clock skew, the clock cycle time is increased Clock skew is reduced by balancing the clock delays|0xF0xF40xF &+) Next . . .Designing a Processor: Step-by-Step Datapath Components and Clocking Assembling an Adequate Datapath Controlling the Execution of Instructions The Main Controller and ALU Controller Drawback of the single-cycle processor design( dEJUInstruction Fetching DatapathHWe can now assemble the datapath from its components For instruction fetching, we need & Program Counter (PC) register Instruction Memory Adder for incrementing PC 6YKYK Datapath for R-type InstructionsControl signals ALUCtrl is derived from the funct field because Op = 0 for R-type RegWrite is used to enable the writing of the ALU resultr{!1>!1$Datapath for I-type ALU InstructionsControl signals ALUCtrl is derived from the Op field RegWrite is used to enable the writing of the ALU result ExtOp is used to control the extension of the 16-bit immediate 2 2&9>1:#Combining R-type & I-type Datapaths  !Controlling ALU Instructions 8Details of the ExtenderTwo types of extensions Zero-extension for unsigned constants Sign-extension for signed constants Control signal ExtOp indicates type of extension Extender Implementation: wiring and one AND gateJJbJNqNAdding Data Memory to Datapath6A data memory is added for load and store instructionsN7 !Controlling the Execution of Load "Controlling the Execution of Store 1"Adding Jump and Branch to DatapathAdditional Control Signals J, Beq, Bne for jump and branch instructions Zero condition of the ALU is examined PCSrc = 1 for Jump & taken Branchdu "" LH2Details of Next PCImm16 is sign-extended to 30 bits Jump target address: upper 4 bits of PC are concatenated with Imm26 PCSrc = J + (Beq . Zero) + (Bne . Zero)l -ff6!Controlling the Execution of Jump 7#Controlling the Execution of Branch * Next . . .Designing a Processor: Step-by-Step Datapath Components and Clocking Assembling an Adequate Datapath Controlling the Execution of Instructions The Main Controller and ALU Controller Drawback of the single-cycle processor design( d'.Main Control and ALU ControlhInput: 6-bit opcode field from instruction Output: 10 control signals for datapath ALUOp for ALU Control$6S5Single-Cycle Datapath + Control Main Control Signals Main Control Signal ValuesrX is a don t care (can be 0 or 1), used to minimize logic #Logic Equations for Control SignalsRegDst <= R-type RegWrite <= (sw + beq + bne + j) ExtOp <= (andi + ori + xori) ALUSrc <= (R-type + beq + bne) MemRead <= lw MemWrite <= sw MemtoReg <= lw PD  ALU Control Truth Table $ Next . . .Designing a Processor: Step-by-Step Datapath Components and Clocking Assembling an Adequate Datapath Controlling the Execution of Instructions The Main Controller and ALU Controller Drawback of the single-cycle processor design d./#Drawbacks of Single Cycle ProcessorLong cycle time All instructions take as much time as the slowest Alternative Solution: Multicycle implementation Break down instruction execution into multiple cycles20 d6* 60Multicycle ImplementationJBreak instruction execution into five steps Instruction fetch Instruction decode and register read Execution, memory address calculation, or branch completion Memory access or ALU instruction completion Load instruction completion One step = One clock cycle (clock cycle is reduced) First 2 steps are the same for all instructions, 2 24 20 2! / Performance ExampleAssume the following operation times for components: Instruction and data memories: 200 ps ALU and adders: 180 ps Decode and Register file access (read or write): 150 ps Ignore the delays in PC, mux, extender, and wires Which of the following would be faster and by how much? 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PxB ~  H 1 ?xB   H 1 ?xB   H 1 ?EExB   H 1 ?rB   B 1 ?PrB   B 1 ?PrB   B 1 ?H PH rB   B 1 ? P rB   B 1 ?p Pp rB   B 1 ?( P( rB   B 1 ?PrB   B 1 ? P rB   B 1 ?PrB   B 1 ? P rB   B 1 ? P rB   B 1 ?PPPH  0޽h ? a(___PPT10i.ZOw%+D=' = @B +  0L0 P  p(   ~  s * `     s * `x  @,$`H  0޽h ? X(=^___PPT10i.Pؤ`+D=' = @B +*  0L0 &`  (   ~  s * `      B"` `x<$@  0  4 ` $`H  0޽h ? a(f(^(___PPT10>(+1;[D"(' = @B D'' = @BA?%,( < +O%,( < +D' =%(D.' =%(D' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =+4 8?\CB#ppt_xBCB#ppt_xB*Y3>B ppt_x<* D' =+4 8?dCB1+#ppt_h/2BCB#ppt_yB*Y3>B ppt_y<* D' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<* I%(D' =+4 8?\CB#ppt_xBCB#ppt_xB*Y3>B ppt_x<* ID' =+4 8?dCB1+#ppt_h/2BCB#ppt_yB*Y3>B ppt_y<* ID' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<* I|%(D' =+4 8?\CB#ppt_xBCB#ppt_xB*Y3>B ppt_x<* I|D' =+4 8?dCB1+#ppt_h/2BCB#ppt_yB*Y3>B ppt_y<* I|D' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<* |%(D' =+4 8?\CB#ppt_xBCB#ppt_xB*Y3>B ppt_x<* |D' =+4 8?dCB1+#ppt_h/2BCB#ppt_yB*Y3>B ppt_y<* |D' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =+4 8?\CB#ppt_xBCB#ppt_xB*Y3>B ppt_x<* D' =+4 8?dCB1+#ppt_h/2BCB#ppt_yB*Y3>B ppt_y<* D' =%(D.' =%(D' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =+4 8?\CB#ppt_xBCB#ppt_xB*Y3>B ppt_x<* D' =+4 8?dCB1+#ppt_h/2BCB#ppt_yB*Y3>B ppt_y<* D' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<* $%(D' =+4 8?\CB#ppt_xBCB#ppt_xB*Y3>B ppt_x<* $D' =+4 8?dCB1+#ppt_h/2BCB#ppt_yB*Y3>B ppt_y<* $D' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<* $O%(D' =+4 8?\CB#ppt_xBCB#ppt_xB*Y3>B ppt_x<* $OD' =+4 8?dCB1+#ppt_h/2BCB#ppt_yB*Y3>B ppt_y<* $OD' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<* O%(D' =+4 8?\CB#ppt_xBCB#ppt_xB*Y3>B ppt_x<* OD' =+4 8?dCB1+#ppt_h/2BCB#ppt_yB*Y3>B ppt_y<* OD' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =+4 8?\CB#ppt_xBCB#ppt_xB*Y3>B ppt_x<* D' =+4 8?dCB1+#ppt_h/2BCB#ppt_yB*Y3>B ppt_y<* +$(  0   (   ~  s * `     s * `x<$@  0  4 ` $` ^    #  o ,$D  0B  B T DjJ?& }    N 1?^   M concatenation$0( 2H  0޽h ? a(##___PPT10#.}OZ+"LD#' = @B D<#' = @BA?%,( < +O%,( < +D' =%(D.' =%(D' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =+4 8?\CB#ppt_xBCB#ppt_xB*Y3>B ppt_x<* D' =+4 8?dCB1+#ppt_h/2BCB#ppt_yB*Y3>B ppt_y<* D' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<* O%(D' =+4 8?\CB#ppt_xBCB#ppt_xB*Y3>B ppt_x<* OD' =+4 8?dCB1+#ppt_h/2BCB#ppt_yB*Y3>B ppt_y<* OD' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<* O%(D' =+4 8?\CB#ppt_xBCB#ppt_xB*Y3>B ppt_x<* OD' =+4 8?dCB1+#ppt_h/2BCB#ppt_yB*Y3>B ppt_y<* OD' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =+4 8?\CB#ppt_xBCB#ppt_xB*Y3>B ppt_x<* D' =+4 8?dCB1+#ppt_h/2BCB#ppt_yB*Y3>B ppt_y<* D' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =+4 8?\CB#ppt_xBCB#ppt_xB*Y3>B ppt_x<* D' =+4 8?dCB1+#ppt_h/2BCB#ppt_yB*Y3>B ppt_y<* D ' =%(D ' =%(D' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =+4 8?\CB#ppt_xBCB#ppt_xB*Y3>B ppt_x<* D' =+4 8?dCB1+#ppt_h/2BCB#ppt_yB*Y3>B ppt_y<* D' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<* 1%(D' =+4 8?\CB#ppt_xBCB#ppt_xB*Y3>B ppt_x<* 1D' =+4 8?dCB1+#ppt_h/2BCB#ppt_yB*Y3>B ppt_y<* 1D' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<* 1E%(D' =+4 8?\CB#ppt_xBCB#ppt_xB*Y3>B ppt_x<* 1ED' =+4 8?dCB1+#ppt_h/2BCB#ppt_yB*Y3>B ppt_y<* 1ED' =%(D' =%(D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* +  0L0   <(   ~  s * `   ~  s *x `x  H  0޽h ? X(=^___PPT10i.'`+D=' \= @B + # 0L0 $ <(   ~  s * `   ~  s *\ `  H  0޽h ? X(=^___PPT10i.D`+D=' \= @B +Q  0L0 PP ms `O(      `, 8c 8c1 ? `"  ~  s * `   &8   o x"    B##jJ"` =  G Data Memory 0 B    C xp 1?"` .'  @ Address 0      C xH1?"` G  YData_in0  B   Z D>?    C xD1?"`& "  \Data_out 0   B   Z D>? B   Z D>?<} } B  Z D1? JB  Z D1? J   C x1?"`Y J ]MemRead 0     C x@1?"`J ^MemWrite 0   B  B T DjJ? 9    C x1?"` ] m  ; 320  B  B T DjJ? :     C x1?"` a o  ; 320  B  B T DjJ?W` r    C x1?"`= `  ; 320  L c @   # w     3 r#1?"` R ; 320     T jJ?-  @    # l("1?"`f    AAddress0 2 B   T D>?c s - s    # l`+1?"` S  G Instruction 0( 2     # l8/1?"` #  LInstruction Memory0  B   T D>? ~B  B N DjJ?    3 r21?"`c  V  ; 320  ~B  B N DjJ? V L * 3 # }x" 4  HG0*jJ?0*0 5 B  `h71?"`0*0 Am u x  Fc 6 B  `:1?"`0; 50 B  7 B  `?1?"`00 51 B B 8 T D>?0B 9 T D>?-P-B : T D>?0B ; T D1?i0i <  3 rC1?"`1 Bselect 0  8 N  p  O 2 ?  Z jJ? 1 @  # lGxaxa1?"` >Extend PBB A  Z D>?)) B  C xpL1?"`" ; 320  B C B T DjJ?@B D Z DԔ?N#$ E  C xO1?"`j :160  B F B T DjJ?@B G Z D1?0 H  C xS1?"`1 [ExtOp 0  QL CmC  I # F o J  <W##jJ"`@  E Registers 0 B  K  3 r\1?"`W  ; RA0   L  3 r`1?"`  =  :RB0  B M  T Do?C   N  3 rd1?"`V  XBusA0  B O  T Do?C  B P  T D>? m B Q T D1?@   R  3 rh1?"` aC  `RegWrite" 0   B S  T D>? m  T  3 r8m1?"` =  XBusB0  B U  T Do?C   V  3 ro1?"` Y   :RW0  B W T D>?@ & ~B X B N D1?` }: ~B Y B N D1?` } ~B Z B N D1?` }  [  3 rxt1?"`C  : 50   \  3 r,y1?"`CV   : 50   ]  3 r4w1?"`C   : 50  ~B ^ B N DjJ? :  _  3 r`1?"`  ; 320  ~B ` B N DjJ?   a  3 r1?"`s   ; 320  ~B b B N DjJ? /  c  3 r؇1?"`/ &  ; 320   d  3 r1?"` #  XBusW0  LL V]  e #   f  T@jJ"`  <PC0B B g  T D>?V   h  3 r1?"`Vp ; 320  ~B i B N DjJ?r B j  T D>? ]  k  3 r1?"`p ; 320  ~B l B N DjJ? !8 0MW s M0W* "  c BC DE F*jJ? p ` @`S" M: #  # l$xaxa1?"` =A L U PBB $  Z D>?0B %  Z D>?0B & Z D>?B ' Z Do? (  C x1?"` G ALU control 0    )  C x1?"`nW B ALU result 0   B *  Z D1? +  C x1?"`s @zero 0   ,  C x1?"`0 ; 320  B - B T DjJ?Je .  C xD1?"`1M ; 320  B / B T DjJ?Kf 0  C xD1?"`4\ ; 320  B 1 B T DjJ? (B 2 B T D1?n:WB q  T D1?VV r  3 r̸1?"` Doverflow 0   H  0޽h ? X(=^___PPT10i.5`+D=' \= @B +   0L0     (   ~  s * `x  ~  s *Ľ `   D 8  m   @ p   3 rjJ?"` P BRegister 0 2 lB  B <1? 6 7fB  B 6jJ?hMk   Zxaxa1? h ]Data_In 0 BB   Z D)?PB   Z D)?m fB  B 6jJ?hh  R    `Z jJ? p p   Zxaxa1?"`   AClock 0 BlB   <1?"!!   Zxaxa1?b H Write Enable 0  B    f1?m >n bits0    Zxaxa1? g  ^Data_Out 0  B    f1? m  >n bits0 H  0޽h ? X(=^y___PPT10Y+D=' \= @B +A  0L0 D<!%& (   ~  s *l `m    Zxaxa1?O <RW0   ZLxaxa1?p <RA0   Z,xaxa1? <RB0 ~  s * `   8 `  & f6@    B##jJ"`"?  S Register File*0( @B   C xD1?"`",7 ; RA0     C x1?"`=o,  :RB0  B   Z Do?"   C x1?"`6 XBusA0  B   Z Do?"B  Z D1?,@ ,    C x( 1?"`w `  `RegWrite" 0      C x1?"`   XBusB0  B   Z Do? "    C xd1?"`=9 ,  :RW0  B  Z D>?@ C B  B T D1?B  B T D1?B  B T D1?r     C x41?"`m : 50     C x1?"`6 : 50     C x1?"` s  : 50  B  Z D>?B   Z D>?V V B  B T DjJ?   C x`#1?"`m/ ; 320  B  B T DjJ?9 s    C x'1?"`.9  ; 320  B  B T DjJ?   !  C xP,1?"`  s&  ; 320   "  C xT*1?"`k Z#  XBusW0   #  C xT21?"`r= F  =Clock0  B $  Z D1?v "v R %   `Z jJ?"= W H  0޽h ? X(=^___PPT10e.+D=' \= @B +MH  0 dG\G"nT (  F(  T  T  BCDE F @S" s T  BCDE FA@S" s} 2 r T S 7 `   dB T <D> f dR T <Z1F !T  ZBTCDE F>TT@"`  'T TA1S"`? ?  NBusA 2 T NG1"` P 4R1(2jR T BZ1Z"  T NK1"`C  4R2(2jR  T BZ1pZ T NN1"`$   5R31(2jR T BZ1Q Z  +T  BCrDE FAA>r@"`jD ,T  BCrDE F>r@"` j$  -T ZS1S"`?  z  ;. . .2 .T ZX1S"`??   NBusW 2 6T  `U1 "`  9Decoder(2^B 7T 6Do < <  8T ZxY1 S"`?B 4RW(2XB ;T @ 0DjJ  6i  >T ZXc1 S"`?j b  55(2dr ?T <1BXB @T 0DdB AT <DPRB BT s *DYYdB CT <DRB KT s *D9RB LT s *DPPdr OT <1OXB PT 0D^B QT 6DP^B ST 6D88dr UT <1"  XB VT 0D} } dB WT <D} P} dB YT <D   ZT Zk1S"`?I  5Clock 2RB [T s *DwRB \T s *DP ]T Nq1S"`?Iz  RRegWrite 2  eT c B{CdDEFAdTdT{ @c"$`  fT c B{C7DEFA{7T7T @c"$`  8  gT C BqCDE FAqq@S"  hT Zxu1S"`?Y@b  9. . .2 iT Zz1S"`?V DR0 is not used lT  BCDEF> @"`j dR nT <Z1f  f pT Tx~1S"`?I~ NBusB 2dR rT <Z1R F5 dR vT <Z12FdB yT <D> f  zT  ZBTCDE F>TT@"`  dR {T <Z1,f   dB |T <D>| f }  }T  ZBTCDE F>TT@"`}  dR ~T <Z1 f   &T s BTCDE F>TT@"`V/dB T @ <D>Fv v  T T1S"`? E 5"0"(2dR T <1mRB T s *D>VdB T @ <D>F T T1S"`?E 5"0"(2L   T # / s 2T  TP1S"`?   4RA(2 0T  Z̑1"`  9Decoder(2lB 1T  <ZDoI J fB 9T 6DjJ 6w M DEFArr> @S" s8 L   T #  ps T  Tl1S"`?   4RB(2 T  T1"`  9Decoder(2fB T  6ZDoI J `B T 0DjJ 6w M T  T1S"`?w   55(2 T  BCDEF ^^ @S" s5  T  BrC>DEF rr> @S" sxRB T @ s *DjJl *  T Tئ1S"`? Vl  632(2RB T @ s *DjJ( T T1S"`?& 632(2RB T @ s *DjJ T T1S"`?% 632(2RB T @ s *DjJl   T T1S"`? $l  632(2RB T @ s *DjJO    T Tط1S"`? F O  632(2RB T @ s *DjJo   T Tл1S"`? E o 632(2RB T @ s *DjJ  " T Tȿ1S"`? D  632(2dR T <1 m T s BTCDE F>TT@"`V v | dB T <D> v dB T <D> v dB T <D> / dB T <D>/vB T ND> v j  T  B7CDEF '7'7 @S" s_vB T ND>PRB T @ s *DjJ   T T1S"`? C  632(2RB T @ s *DjJv T T1S"`? Vv 632(2 T TX1S"`?G @Tri-state bufferH T 0޽h ? 33___PPT10i.2+D=' \= @B +(  0 ?7#$d (  d r d S Ym  r d S \ `   8  s #d s rR d  BZjJj/fB d  6DԔjfB d  6DԔ@`B d  0D1j`B d 0D1f6`B  d  0D1M/`B  d  0D6U6"  d  T "` O-H QData_in 2  d  T|"`OH RData_out 2   d  Tl"`s]? <Enable(2 8  / 3 $d / 3ZB d  s *D rR d  BZjJ7P 3fB d  6DԔ 7 fB d  6DԔ 7 ZB d  s *D ( fR d  6MU  f2 d  6z( U rR d  BZjJ7/  " d   BCDEF5%DD @c"$`   d  # B[C DEFAAԔ[[   @ 1 xB d  HDԔ0   d  TH"` /   6Data_0 2 d  T"` O 2 6Data_1 2  d  T"`)? 3"  6Output 2 !d  TP"` :Select 2H d 0޽h ? 33___PPT10i. ?+D=' \= @B +P  0 OO"nX 0 O(  X x X c $ `    X c BCDE FA @c"$` XB X 0D  }}  uX c BCDEFAA>  @R l B iX Z D>?  A L 2 V Z9  >X #  8 & l 8X B <GIjJ` V Z9 2 9X  CENHE.JQjJ `T`T`T`T2 V ` 9 j @X @ BGIjJ  , & B MX Z D>? %j" RX BG0*jJ f  SX C x 1? "`2 =0 0   TX C xh1? "`v =1 0  B YX Z D>?  ZX C x1? "`B =2 0   [X C x1? "`   =3 0  B ^X Z D>?  % E j" _X BG0*jJ  I `X C xd1? "` I  =0 0   aX C x|1? "` IU  =1 0  B cX Z D>? E % IE  eX C x1? "` I!  =2 0   fX C x8#1? "`f I  =3 0  jR gX BZjJ   y ! d2 hX <jJ  y  jX c BCDEF> [ @"` E jB kX BD> l % l dr ]X <jJ  , & B lX # l D>?  L ,   nX  BC'DE F> ''@"`L , f B oX # l D>?  </  qX  BC'DE F> ''@"`% <, pB sX HD>  <( B tX # l D>? ( L , ( j vX BjJ b % wX C x*1? "` p  D Logic Unit 0   xX  BCDE FAjJ @S" L  yX #  _`B zX  3 r/1?"`, B 2$0  ~B {X B N DjJ?=, |X C xX31? "` }Y `"AND = 00 OR = 01 NOR = 10 XOR = 11"#0 #j }X @ BH*jJ  Y ~X S ~81? "` =d KLogical Operation0  X C x<jJ? "`f  ?Shifter0  X c BCDEF>  @ X  BCDE FjJ @S"  L  X #  p X  3 r?1?"`, B 2$0  ~B X B N DjJ?=, X C xC1? "`b|@ b$None = 00 SLL = 01 SRL = 10 SRA = 11"%0 %j X @ BH*jJ @ X S ~H1? "`=4 IShift Operation0  X  BC'DE F> ''@"`]<f & XB ?X 0D> % / % B X Z D>?   %X C xM1? "`wv 9A0 L  0X #  , #X  C x@Q1?"`, ? 32 0  B &X B T DjJ?=,B 1X Z D>? h ( i L  2X #   2  3X  3 r`V1?"`, ? 32 0  ~B 4X B N DjJ?=, 5X C xZ1? "`pw 9B0 ZL  }  EX #   (  =X B <GIjJC"? t } r CX B BGIjJ } 2 DX  CENHE.JQjJ `T`T`T`T } L   GX #   % * X  c BC DE F*jJ? p ` @`S"   X  # l_xaxa1?"`Cn6  C A d d e r  P B  FX  BCGDEF G @c"$` }  HX C x|d1? "`f q2 Hc0*0  L  IX #  o,R  JX  3 ri1?"`, ? 32 0  ~B KX B N DjJ?=,RB  }} d2 X <jJ  g  X C xx1? "`   Bzero"0 B X Z D>? dB X <D &c^B X 6D cc  X C x1? "` t  Foverflow" 0  $ X C x1? "`dC) n4SLT: ALU does a SUB and check the sign and overflow 50 5RB X s *DjJ z H X 0޽h ?/ 9X DX  33___PPT10i.2+D=' \= @B +  0L0  !#$ (   ~  s *ȓ `   ~  s * `x  \8 ~  $ C B  Z D1?( (F    C x@1?"`F   ^MemWrite 0   B  Z D1?E EF    C x1?"`F   ]MemRead 0     BH##jJ"`  E Data Memory 0 B   C x@1?"`= K  ?Address0     C xػ1?"`   YData_in0  B   Z D>?w w    C x1?"`@   \Data_out 0   B   Z D>?@ A B   Z D>?v ~v B  B T DjJ? Y :    C x1?"` oY  ; 320  B  B T DjJ?"# <]    C x1?"` q#  ; 320  B  B T DjJ?Y     C x1?"` /Y  ; 320  B  Z D1?& ' R    `Z jJ? a    C xd1?"` }  =Clock0  T ? 3-  # ~   3 r1?"`j '  ; 320     T jJ?& M-   # lD1?"`B }  AAddress0 2 B   T D>??C %C    # l\1?"`  /}  G Instruction 0( 2     # l`1?"`&} 0- LInstruction Memory0 B   T D>?LD 3D ~B ! B N DjJ?' a  "  3 r1?"`[ &  ; 320  ~B # B N DjJ?w& ` H  0޽h ? X(=^___PPT10e.+D=' \= @B +Z  0 qi  (   ~  s *4 `      B "` "P   E8      T F 3B   # e 2   T jJ?F 3B    # ljJ?S"`?F 3B  MCombinational logic0 2   C xHjJ?"`   E Register 1 0 2 B  # l DjJ?A A R   Z jJ?  u    C xjJ?"` n  E Register 2 0 2 B  Z DjJ?  R   Z jJ? 8 B   Z D>?y ey B   Z D>? y y B  B T DjJ?     3 rP1?"`3   ?clock0 2   s 0e0e    B' CDE F( jJ 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||] ] ' @S" , B  Z D1?AAB   Z D1?""B  Z D1?     3 r( 1?"`}I E rising edge 0 2    3 r1?"`<I  F falling edge 0 2 >  Tֳֳ ?"`&f We assume edge-triggered clocking All state changes occur on the same clock edge Data must be valid and stable before arrival of clock edge Edge-triggered clocking allows a register to be read and written during same clock cycle 2   wh@`H  0޽h ? a(___PPT10i.P:+D=' \= @B +  0   (   ~  s *. `   ~  s *@ `x     fjJ?"`  0 @Tcycle e" Tclk-q + Tmax_comb + Tsz!0 BJBJBJBJ6 F L JM    # M  T F 3B   #  9 2   T jJ?F 3B    # l89jJ?S"`?F 3B  MCombinational logic0 2   3 r=jJ?"`JM0s  E Register 1 0 2 B   f DjJ?t  R   T jJ?: s    3 rAjJ?"` M s  E Register 2 0 2 B  T DjJ?P t P  R   T jJ? : s B   T D>?0B   T D>?  ~B  B N DjJ?g P     # lF1?"`M:   ?clock0 2  s 0e0e    B CDE F( jJ 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||VV @S"  8 { B  Z D1? $ B  Z D1? J J $   3 rK1?"` z  ]  F writing edge 0 2 L     #      # lxP1?"`   dTclk-q(0`    # lT1?"`  g Tmax_comb( 0`      # lY1?"` Q  FTs(0`    # llV1?"`P   `Th(0` ]  T|ֳֳ ?"`9 YK ?Tclk-q : clock to output delay through register Tmax_comb : longest delay through combinational logic Ts : setup time that input to a register must be stable before arrival of clock edge Th: hold time that input to a register must hold after arrival of clock edge Hold time (Th) is normally satisfied since Tclk-q > Th @ ( + T W   l* Vh@`H  0޽h ? a(___PPT10i.P +D=' \= @B +  0   (   ~  s *n `      Bo"` `m     Z,ujJ?"`z T  hTcycle e" Tclk-q + Tmax_combinational + Tsetup+ Tskew50 BJBJBJBJ BZH  0޽h ? a(___PPT10i.P@X+D=' \= @B + " 0L0 # <(   ~  s * `   ~  s * `  H  0޽h ? X(=^___PPT10i.D`+D=' \= @B +E  0L0 22@!69 e2(      `ԡ 8c 8c1 ? `0   ~  s *| `     TjJ?  j ,$@ 0 The least significant 2 bits of the PC are  00 since PC is a multiple of 4BL( v2+$  T`jJ?W  ,$D 0 l4Datapath does not handle branch or jump instructions50 5K  TjJ?j,$@ 0 5Improved datapath increments upper 30 bits of PC by 1B6( v2 a  y  #  ,$D 0   TjJ"` M <PC0B     0e0e    BGCDEF  > 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||vGvG @ V "   S 0e0e    BCDE F > 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||@"`@     3 r1?"` `  ; 320     T jJ? v   # l1?"` c  AAddress0 2 B   T D>?L     # l1?"`6& Y  G Instruction 0( 2     # lX1?"` < LInstruction Memory0  B   T D>?v} y} ~B  B N DjJ?`     3 rL1?"`~ k  ; 320  ~B  B N DjJ? 2+    3 rD1?"`- ]  ; 320  ~B  B N DjJ?# ,A B   T D>?     3 r1?"` k#  ; 320  ~B  B N DjJ?# 2]    # l1?"` =  =4 0 2 T     #   *   c BC DE F*jJ? p ` @`S"       fxaxa1?"`V   =A d d PB   3 r1?"`IV   Anext PC0  Al s  8 s ,$D 0 !  C xH1?"` /`  ; 320   "  Z jJ?,  #  3 rd1?"`` c  AAddress0 2 B $  Z D>? ,  %  3 r<1?"`&   G Instruction 0( 2   &  3 r1?"`{ t LInstruction Memory0  B '  Z D>?} } B ( B T DjJ?`   )  C x81?"`q~   ; 320  B * B T DjJ? +  +  C xP1?"` 2]  ; 300  B , B T DjJ?# A T    - # g  .  TjJ"` `   >PC 0B  /  TjJ"`  `  <000BB 0 # l D>?"@ "  1  C xpjJ?"`Z @  E +1&0  2  C x 1?"`> &  ; 300  B 3 B T DjJ? =   4   0e0e    BC DEF > 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||W   @ "  5  T 1? ]  OImproved Datapath"0  6  C x1?"`s   Anext PC0   7 TjJ"`  ` ,$D 0 @00"0FH  0޽h ? X(=^___PPT10h. e`+LD\' \= @B D' = @BA?%,( < +O%,( < +D' =%(D' =%(D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* D8' =%(D' =%(D@' =A@BB BB0B%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* D@' =A@BB BB0B%(D' =1:Bvisible*o3>+B#style.visibility<*7 %(D' =-o6Bdissolve*<3<*7 D+' =%(D' =%(D@' =A@BB BB0B%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<*8 %(D' =-o6Bdissolve*<3<*8 D' =%(D' =%(D@' =A@BB BB0B%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* ++0+ 0 ++0+ 0 ++0+ 0 ++0+7 0 +p  0 II`!RR ,I(   ~  s *( `     s *8d `x<$  0  0@ $`L Pz P   # C*   T :0e0ejJ?"`Pz   OOp600 UBJ   T80e0ejJ?"`z  ORs500 UBJ   T4@0e0ejJ?"` z P  ORt500 UBJ   TD0e0ejJ?"`P z   ORd500 UBJ   TH0e0ejJ?"`z P  Rfunct600 UBJ   TdM0e0efjJ?"` z   Osa500 UBJ)     # ~ L,$D 0*   c BC DE F*jJ? p ` @`S" r    fQxaxa1?"`K  =A L U PBv T  r9  #  r9    0e0e    BCsDEF > 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||ss @ r    0e0e    BCVDEF > 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||VV @ Or   3 rV1?"` ; 320  ~B  B N DjJ?9   3 rZ1?"`2 ; 320  ~B  B N DjJ?2l 9  #  ,$D  0B   T Do?   3 r^1?"`9 _ALUCtrl"0  ~B  B N D1?<4 k    #  ,$D 0B   T D1?5 5    3 rc1?"`k   `RegWrite" 0        #   ,$D 0   <h##jJ"`   E Registers 0 B    3 rl1?"` l  ; RA0     3 rq1?"`   :RB0     3 ro1?"`i kl  XBusA0   !  3 rw1?"`i ol  XBusB0   "  3 rh{1?"`   :RW0   #  3 r1?"`i 8l  XBusW0  gL _  $ #  %  3 r1?"`&  ; 320   &  T jJ? '  # l}1?"`n AAddress0 2 B (  T D>?l )  # ld1?"`VyR G Instruction 0( 2   *  # lЍ1?"`9\ LInstruction Memory0  B +   ` D>?_ ~B , B N DjJ?6 -  3 r1?"`5 ; 320  ~B . B N DjJ?5R /  3 r$1?"`M ; 300  ~B 0 B N DjJ?LT    1 # l 2  TjJ"` `   <PC0B  3  TjJ"`  `  <000BB 4  f D>? 5  3 r(jJ?"`O6 E +1&0  6  3 rȤ1?"`jS ; 300  ~B 7 B N DjJ?  8   0e0e    BC DEF > 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||W   @/~B 9 B N D>?_ _ & _ 2  : # 2 ,$@ 0B ;  T Do?_  B <  T Do?_ o o~N  2  =   2 ~B > B N D1?c   ?  3 r1?"`F 2  : 50    @  3 r1?"` 2)  TRs0  ~B A B N D1?c Q  B  3 rԲ1?"`F  Q : 50    C  3 r̶1?"` ) Q TRt0   _  T D #  T,$D 0B E  T Do?_ 8 8N   T F    T~B G B N D1?c  T H  3 rT1?"`F   : 50   I  3 r1?"` )  :Rd0    Ft  J #  t ,$D  0 K  3 r1?"`F B ALU result 0    L  3 r1?"`" ; 320  ~B M B N DjJ?S  N   0e0e    BcC@DEF > 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||cc@@ @ 4\t  O NjJ?S  ,$@ 0 dRA & RB come from the instruction s Rs & Rt fields 30( 23,$ P NxjJ?F  & ,$@ 0 VRW comes from the Rd field 0( 2B Q NjJ?  ,$@ 0  ALU inputs come from BusA & BusB !0( 2!,/ R N,jJ?F & ,$@  0 }ALU result is connected to BusW 0( 2 H  0޽h ? a('&&___PPT10%.Pm+7aQD$' \= @B Dv$' = @BA?%,( < +O%,( < +Df' =%(D' =%(D@' =A@BB BB0B%(D' =1:Bvisible*o3>+B#style.visibility<*O %(D' =-o6Bdissolve*<3<*O D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<*: %(D' =-o6Bdissolve*<3<*: D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* D+' =%(D' =%(D@' =A@BB BB0B%(D' =1:Bvisible*o3>+B#style.visibility<*P %(D' =-o6Bdissolve*<3<*P D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<*D %(D' =-o6Bdissolve*<3<*D D+' =%(D' =%(D@' =A@BB BB0B%(D' =1:Bvisible*o3>+B#style.visibility<*Q %(D' =-o6Bdissolve*<3<*Q D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* D+' =%(D' =%(D@' =A@BB BB0B%(D' =1:Bvisible*o3>+B#style.visibility<*R %(D' =-o6Bdissolve*<3<*R D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<*J %(D' =-o6Bdissolve*<3<*J Ds' =%(D' =%(D@' =A@BB BB0B%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* D@' =A@BB BB0B%(D' =1:Bvisible*o3>+B#style.visibility<* R%(D' =-o6Bdissolve*<3<* RD3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* D+' =%(D' =%(D@' =A@BB BB0B%(D' =1:Bvisible*o3>+B#style.visibility<* R%(D' =-o6Bdissolve*<3<* RD3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* ++0+ 0 ++0+O 0 ++0+P 0 ++0+Q 0 ++0+R 0 +t  0 PPp!\\ DP(      B"` `      B "` `\<$ 0  0 $` L P P   # }   T0e0ejJ?"`P   OOp600 UBJ   T0e0ejJ?"`  ORs500 UBJ   T0e0ejJ?"` P  ORt500 UBJ   Th0e0efjJ?"`P P  W immediate160 0 U BJ   #  D,$D  0   3 r1?"` _ALUCtrl"0  B   T Do?~B  B N D1? 4 O    # ] a,$D  0B   T D1?     3 rL1?"`O   `RegWrite" 0   gL C !   # zd4    3 rd 1?"`  ; 320     T jJ?z   # l$1?"`n AAddress0 2 B   T D>?P   # lT)1?"`:]R G Instruction 0( 2     # l,1?"`@ LInstruction Memory0  B    ` D>?zC ~B  B N DjJ?6   3 rt01?"`5o ; 320  ~B  B N DjJ?6   3 rl41?"`1 ; 300  ~B  B N DjJ?0T     # P   T8jJ"` `   <PC0B    T 7jJ"`  `  <000BB   f D>? !  3 r@jJ?"`3 E +1&0  "  3 rE1?"`j7 ; 300  ~B # B N DjJ?  $   0e0e    BC DEF > 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||W   @~B % B N D>?C C !   7 & #  ,$D 0B '  T D>?m 7B (  T Do? m o~B ) B N DjJ?   *  3 rlJ1?"`m   ; 320  ~B + B N D1?G Qd  ,  3 rN1?"`*  Q : 50   C n  - # b4 ,$D 0\N  n  .   n  /  <4S##jJ"` n  E Registers 0 B  0  3 r,W1?"` l  ; RA0   1  3 rU1?"`   :RB0   2  3 r^1?"`M kP  XBusA0   3  3 r@b1?"`M oP  XBusB0   4  3 r|f1?"`   :RW0   5  3 rd1?"`M 8P  XBusW0  N C 2 T 6  C 2 TB 7  T Do?C  B 8  T Do?C 8 8~B 9 B N D1?G d  :  3 r0n1?"`* 2  : 50    ;  3 rr1?"` 2  TRs0  ~B < B N D1?G d T =  3 rdv1?"`*   : 50    >  3 r|z1?"`   TRt0  1    ? # G Q n ,$D 0B @  T D1? W   A  3 r}1?"`  W  ]ExtOp"0   C *  B # 4XT ,$D 0N 9 C  9 D  3 r1?"` ; 320  ~B E B N DjJ?9@N C *  F  C * T  *t  G #  *t  H  3 rx1?"`z* B ALU result 0    I  3 r1?"` ; 320  ~B J B N DjJ?S  K   0e0e    BcC@DEF > 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||cc@@ @ 4@t T m V L # m V M   0e0e    BCVDEF > 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||VV @m OV N  3 r@1?"`2 ; 320  ~B O B N DjJ?2lT Vv P # Vv* Q  c BC DE F*jJ? p ` @`S" Vv R   f̔xaxa1?"`Kv  =A L U PB S   0e0e    BvCWDE F Ԕ 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||WvW@C !  T   0e0e    BCDEF > 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E|| @m V! T  oV  U #  l 2 V  T jJ? oV  W   fxaxa1?"` :  @Extender  P B~B X B N DjJ?*  G >  Y  3 rq1?"`   =Imm160    Z NjJ? x ,$@ 0 n2Second ALU input comes from the extended immediate 30( 23( [ N|jJ?  ,$@ 0 vRB and BusB are not used 0( 2M \ ZjJ?"` { ,$@ 0 #RW now comes from Rt, instead of Rd $0( 2$H  0޽h ? a(##___PPT10#.Pm+P-D"' \= @B D;"' = @BA?%,( < +O%,( < +D+' =%(D' =%(D@' =A@BB BB0B%(D' =1:Bvisible*o3>+B#style.visibility<*\ %(D' =-o6Bdissolve*<3<*\ D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<*- %(D' =-o6Bdissolve*<3<*- D+' =%(D' =%(D@' =A@BB BB0B%(D' =1:Bvisible*o3>+B#style.visibility<*Z %(D' =-o6Bdissolve*<3<*Z D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<*B %(D' =-o6Bdissolve*<3<*B D+' =%(D' =%(D@' =A@BB BB0B%(D' =1:Bvisible*o3>+B#style.visibility<*[ %(D' =-o6Bdissolve*<3<*[ D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<*& %(D' =-o6Bdissolve*<3<*& Ds' =%(D' =%(D@' =A@BB BB0B%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* D@' =A@BB BB0B%(D' =1:Bvisible*o3>+B#style.visibility<* 5%(D' =-o6Bdissolve*<3<* 5D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* D+' =%(D' =%(D@' =A@BB BB0B%(D' =1:Bvisible*o3>+B#style.visibility<* 5n%(D' =-o6Bdissolve*<3<* 5nD3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* D+' =%(D' =%(D@' =A@BB BB0B%(D' =1:Bvisible*o3>+B#style.visibility<* n%(D' =-o6Bdissolve*<3<* nD3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<*? %(D' =-o6Bdissolve*<3<*? ++0+ 0 ++0+Z 0 ++0+[ 0 ++0+\ 0 +3  0 [[!`` B[(   ~  s * `     TTgֳgֳ ? d,$@ 0 K'Control signals ALUCtrl is derived from either the Op or the funct field RegWrite enables the writing of the ALU result ExtOp controls the extension of the 16-bit immediate RegDst selects the register destination as either Rt or Rd ALUSrc selects the 2nd ALU source as BusB or extended immediateD/,   &'0, $`E  NhjJ? ,$@ 0 #A mux selects RW as either Rt or Rd $0( 2$,  NjJ? ,$@ 0 eAnother mux selects 2nd ALU input as either source register Rt data on BusB or the extended immediate6f0( 2 O>1    #  ,$D 0B   T Do?I   3 r1?"`F _ALUCtrl"0  ~B  B N D1?d 4 2 ` d  # `V d,$D  0B   T D1?  d   3 r1?"`2 `  `RegWrite" 0   1 f  q  #  q,$D  0B   T D1?  q   3 r1?"`f   ]ExtOp"0  A@L }#W   # }W     0e0e    BCwDEF > 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||VVww @P mS     0e0e    BcC@DEF > 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||cc@@ @ #7    0e0e    BvCWDE F Ԕ 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||WvW@&      0e0e    BCVDEF > 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||VV @P Vg*   c BC DE F*jJ? p ` @`S" Vvo    fxaxa1?"`v =A L U PB   3 r 1?"`sS# B ALU result 0      3 rl1?"` ; 320  ~B  B N DjJ?/   3 r< 1?"`i ; 320  ~B  B N DjJ?   <<##jJ"` eQ  E Registers 0 B    3 r41?"` /  ; RA0     3 r1?"`   :RB0     3 r !1?"`0 .3  XBusA0  B   T D>?P LSM !  3 r$%1?"`0 3  XBusB0  B "  T Do?& h hB #  T Do?& 0 0B $  T Do?F 4 4 %  3 r)1?"`  m :RW0  ~B & B N D1?* KG  '  3 r`.1?"` c K : 50  ~B ( B N DjJ? 0 j )  3 r21?"`m  0 ; 320   *  3 r01?"`0 3 n XBusW0   +  3 r91?"`{L ; 320   ,  T jJ?e] -  # lT=1?"`1 AAddress0 2 B .  T D>?3 /  # l@1?"`@ G Instruction 0( 2   0  # l|D1?"`e# LInstruction Memory0  B 1   ` D>?]& ~B 2 B N DjJ? 3  3 rH1?"`Rk ; 320  ~B 4 B N DjJ?k 5  3 rL1?"`d ; 300  ~B 6 B N DjJ?T    7 # 3 8  T? ;  3 rYjJ?"` E +1&0  <  3 rW1?"`- ; 300  ~B = B N DjJ?nf  >   0e0e    BC DEF > 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||W   @}~B ? B N D>?& b&   @  3 rha1?"`}  K TRs0  ~B A B N D1?* G N B  3 rf1?"` c  : 50   C  3 r,j1?"`C P  :Rd0  T  oV  D #  pO W 2 E  T jJ? oV  F   fmxaxa1?"` :  @Extender  P B~B G B N DjJ? *   H  3 rDr1?"`} W  =Imm160    I  3 rb1?"`}   TRt0  B J T D>?V~B K B N DjJ?   L  3 ry1?"` 6 ; 320  B M  T Do?&  ~B N B N D1?` }  O  3 rD}1?"`C  7 : 50  " P  S 0e0e    BWCWDE F o 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||WWW@"`| 0   jF  Q # j | ,$D 0x" R  HG0*jJ? jF  S B  `́1?"` jF  Am u x  Fc  T B  `1?"` wF  50 B  U B  `1?"` F  51 B 2 |   V #  ,$D 0B W T D1?  T X  3 r1?"`| 7  ^RegDst"0  2  Y # n ,,$D 0B Z T D1? [  3 rX1?"` ^ALUSrc"0    jF  \ # 9 ,$D 0x" ]  HG0*jJ? jF  ^ B  `L1?"` jF  Am u x  Fc  _ B  `1?"` wF  50 B  ` B  `1?"` F  51 B H  0޽h ? a()(!(___PPT10(.Px+9De'' Z= @B D '' = @BA?%,( < +O%,( < +D+' =%(D' =%(D@' =A@BB BB0B%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<*Q %(D' =-o6Bdissolve*<3<*Q D+' =%(D' =%(D@' =A@BB BB0B%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<*\ %(D' =-o6Bdissolve*<3<*\ DY' =%(D' =%(D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<* I%(D' =-o6Bdissolve*<3<* ID3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* D' =%(D' =%(D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<* Ix%(D' =-o6Bdissolve*<3<* IxD3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* D' =%(D' =%(D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<* x%(D' =-o6Bdissolve*<3<* xD3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* D' =%(D' =%(D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<*V %(D' =-o6Bdissolve*<3<*V D' =%(D' =%(D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<* (%(D' =-o6Bdissolve*<3<* (D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<*Y %(D' =-o6Bdissolve*<3<*Y +p+0+ 0 ++0+ 0 +W  0 P#t (  t UMz V M t  % Y,$@ 0B t  T Do?"   t   0e0e    BCwDEFf > 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||VVww @S" L c O   t   0e0e    BcC@DEFf > 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||cc@@ @S"  -  t   0e0e    BvCWDE Ff Ԕ 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||WvW@S" "   t   0e0e    BCVDEFf > 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||VV @S" L  R] *  t  c BC DE F*jJ? p ` @`S" Rx re   t   fxaxa1?"` r  =A L U PBB t  T Do??   t  3 r1?"` <  _ALUCtrl"0   t  3 r1?"`oI B ALU result 0    t  3 r1?"` x  ; 320  ~B t B N DjJ? %  t  3 rx1?"`_   ; 320  ~B t B N DjJ?  ~B t B N D1?Z w  t  <##jJ"` [ M  E Registers 0 B  t  3 r1?"` %  ; RA0   t  3 r1?"` ~  :RB0   t  3 r1?"`, $ /  XBusA0  B t  T D1? Z  t  3 r1?"` V  d RegWrite = 1" 0   B t  T D>?L B O C  t  3 r@1?"`, / }  XBusB0  B t  T Dfo?"^ ^ B t  T Do?z& & B  t  T Dfo?B * *  !t  3 r|1?"` c  :RW0  ~B "t B N D1?& A C {  #t  3 r1?"` _ A  : 50  ~B $t B N DjJ? & `  %t  3 rl1?"`i &  ; 320   &t  3 rp1?"`, / d  XBusW0   't  3 rX1?"`wB   ; 320   (t  T jJ?[ Y  )t  # l1?"`'   AAddress0 2  *t  # l1?"`{ <  G Instruction 0( 2   +t  # lD1?"`[   LInstruction Memory0  B ,t   ` Df>?Y " ~B -t B N DjJ?   .t  3 r1?"` Na  ; 320  ~B /t B N DjJ?a   0t  3 r1?"`Z   ; 300  ~B 1t B N DjJ?  T    2t # z /  3t  T jJ"` `   <PC0B  4t  T jJ"`  `  <000BB 5t  f Df>? }  6t  3 rljJ?"`   E +1&0  7t  3 r1?"`#   ; 300  ~B 8t B N DjJ?j\ z  9t   0e0e    BC DEFf > 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||W   @S" s } ~B :t B N Df>?"X "  ;t  3 r1?"`y A  TRs0  ~B t  3 r#1?"`?F   :Rd0  2 ?t  T fjJ? fK M @t   fP'xaxa1?"` K 1 DExtender  P Ff~B At B N DjJ? & B Bt  T D1?  g Ct  3 r|%1?"`b  ]ExtOp"0   Dt  3 r!1?"`y M =Imm160    Et  3 r|21?"`y   TRt0  B Ft T Df>? R ~B Gt B N DjJ?  Ht  3 rD61?"` 2  ; 320  T  jF  It # ` B x" Jt  HG0*jJ? jF  Kt B  `:1?"` jF  Am u x  Fc  Lt B  `>1?"` wF  50 B  Mt B  `lB1?"` F  51 B ~B Nt B N D1?\ y  Ot  3 rF1?"`? - : 50   Pt   0e0e    BWCWDE Ff o 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||WWW@c"$` x&  T  jF  Qt # O x" Rt  HG0*jJ? jF  St B  `J1?"` jF  Am u x  Fc  Tt B  `N1?"` wF  50 B  Ut B  `S1?"` F  51 B B Vt  T Df>?/} ~ ~B Wt  N Dfo?#& z& r t S V `    t NVjJ?kQ DFor R-type ALU instructions, RegDst is  1 to select Rd on RW and ALUSrc is  0 to select BusB as second ALU input. The active part of datapath is shown in green j0( 2  M>E t NbjJ?n Q,$D 0 ,`For I-type ALU instructions, RegDst is  0 to select Rt on RW and ALUSrc is  1 to select Extended immediate as second ALU input. The active part of datapath is shown in green j0( 2  [> iLF    Xt  Y Yt   0e0e    BCwDEF > 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||VVww @S" L O  Zt   0e0e    BcC@DEFf > 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||cc@@ @S"   [t   0e0e    BvCWDE F Ԕ 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||WvW@S" "7  \t   0e0e    BCVDEFf > 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||VV @S" L R* ]t  c BC DE F*jJ? p ` @`S" R,r ^t   fTpxaxa1?"`r =A L U PBB _t  T Do? `t  3 r\t1?"` ~ _ALUCtrl"0   at  3 rx1?"`op B ALU result 0    bt  3 r}1?"` ,  ; 320  ~B ct B N DjJ?   dt  3 r 1?"` ; 320  ~B et B N DjJ?~B ft B N D1?+ gt  <Ą##jJ"` M 5 E Registers 0 B  ht  3 r$1?"`  L ; RA0   it  3 r1?"`  2 :RB0   jt  3 r1?"`, / K XBusA0  B kt  T D1? ~  lt  3 r1?"`  } d RegWrite = 1" 0   B mt  T Df>?L O  nt  3 r1?"`, / 1 XBusB0  B ot  T Dfo?" B pt  T Dfo?B   qt  3 r|1?"`   :RW0  ~B rt B N D1?& C / st  3 r1?"` _  : 50  ~B tt B N DjJ?   ut  3 r1?"`i g  ; 320   vt  3 rĨ1?"`, /  XBusW0   wt  3 rܬ1?"`wi ; 320   xt  T jJ?Y6 yt  # l@1?"` AAddress0 2  zt  # lD1?"`/< G Instruction 0( 2   {t  # l1?"`L LInstruction Memory0  B |t   ` Df>?Y"~B }t B N DjJ?i ~t  3 r1?"`N ; 320  ~B t B N DjJ?O t  3 r`1?"` ; 300  ~B t B N DjJ?GeT    t # ./5 t  TjJ"` `   <PC0B  t  TjJ"`  `  <000BB t  f Df>?d1 t  3 rdjJ?"`~d E +1&0  t  3 r1?"`J ; 300  ~B t B N DjJ?j. t   0e0e    BC DEFf > 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||W   @S" '1~B t B N Df>?" "  t  3 r@1?"`y TRs0  ~B t B N D1?& C  t  3 r1?"` h_  : 50   t  3 r1?"`?P :Rd0  2 t  T jJ? K   t   fxaxa1?"` 8K  DExtender  P F~B t B N DjJ? q& B t  T D1?   t  3 r,1?"`b Q  ]ExtOp"0   t  3 rx1?"`y   =Imm160    t  3 r,1?"`yg TRt0  B t T Df>? R~B t B N DjJ? n  t  3 r1?"` Q2  ; 320  T  jF  t # B x" t  HG0*jJ? jF  t B  `X1?"` jF  Am u x  Fc  t B  `p1?"` wF  50 B  t B  `1?"` F  51 B B t  T Dfo?"nn~B t B N D1?\Py t  3 r1?"`? : 50   t   0e0e    BWCWDE F o 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||WWW@c"$` xNT  jF  t # O  Px" t  HG0*jJ? jF  t B  `1?"` jF  Am u x  Fc  t B  `1?"` wF  50 B  t B  ` 1?"` F  51 B B t  T Df>?/12B t  T Dfo?" z @ R t  z #,$D 0B t T D1?   t  3 r1?"`@ R b RegDst = 1" 0   ~B t B N Dfo?C mz P s t   ,$D 0B t T D1? Q  t  3 r1?"` Qs b ALUSrc = 0" 0   ~B t  N Df>?P  z @  t  k z o,$D 0B t T D1?  J t  3 r1?"`@,  b RegDst = 0" 0   ~B t N Dfo? C ) z P s t    ,$D 0B t T D1?  t  3 r1?"` s b ALUSrc = 1" 0   ~B t N Df>?P c H t 0޽h ? 33qi___PPT10I.܋g+!D' Z= @B D' = @BA?%,( < +O%,( < +D' =%(D' =%(D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<*t %(D' =-o6Bdissolve*<3<*t D' =%(D' =%(D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<*t %(D' =-o6Bdissolve*<3<*t D+' =%(D' =%(D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<*t %(D' =-o6Bdissolve*<3<*t D@' =A@BB BB0B%(D' =1:Bvisible*o3>+B#style.visibility<*t %(D' =-o6Bdissolve*<3<*t D' =%(D' =%(D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<*t %(D' =-o6Bdissolve*<3<*t D' =%(D' =%(D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<*t %(D' =-o6Bdissolve*<3<*t +8+0+t 0 +Z  0 H@$" P(   r  S L/ `   r  S  `   J  <LjJ"` M M ,$D 0 .ExtOp = 0 Upper16 = 0&n   X  <HjJ"`c  ,$D 0 <ExtOp = 1 Upper16 = sign bit&   8  & "  &  N|jJS"`?  \  ;. . .   BC DE FAA  @"`  lr   <fjJ/  @ `B  0D] ]    B$"`   SExtOp 2l   <jJ:    B`jJS"`? &  A Upper 16 bitsn`B   0D    BC DE F  @"` l   <jJ9    BjJS"`? % A Lower 16 bitsn`B   0D `B   0D `B   0D `B   0D" "   NLjJS"`?O {  ;. . .l  B <jJ:    NjJS"`?  7Imm16nlB   <D s s lB !  <D H  0޽h ? 33___PPT10.n+0D' Z= @B D' = @BA?%,( < +O%,( < +D' =%(D' =%(D@' =A@BB BB0B%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* D' =%(D' =%(D@' =A@BB BB0B%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* +p+0+ 0 ++0+ 0 +Q  0 JuBu! t(     Tp2gֳgֳ ? k,:,$  0 Additional Control signals MemRead for load instructions MemWrite for store instructions MemtoReg selects data on BusW as ALU result or Memory Data_out}  b $`\  N 7jJ?y /  ,$D 0 BBusB is connected to Data_in of Data Memory for store instructions C0( 2C$'~  s *< `   ~  s *= `    NKjJ? /  ,$D 0 FA 3rd mux selects data on BusW as either ALU result or memory data_out6G0( 2 B>  yM-s   # !4 ,$D 0   <S##jJ"`yM-s  G Data Memory 0 B     3 rLX1?"`ym @ Address 0       C xd\1?"`R  YData_in0      3 r@`1?"`_ \Data_out 0     y    #  ! ,$D 0T #Z     # <  ~B  B N DjJ?A ^    3 rd1?"`#Z   ; 320  :   S 0e0e    BCDEF  > 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||   @"` y TK *yY   # ! ,$D 0    0e0e    BCDEF > 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E|| @i f  B  T D>?yT V #   # =~B  B N DjJ?     3 rxi1?"`V #  ; 320  *   c BC DE F*jJ? p ` @`S" 1     fmxaxa1?"`/ =A L U PBB   T Do?   3 rr1?"`Fv _ALUCtrl"0     3 rLv1?"` 1  ; 320  ~B  B N DjJ?  B  T D>?i  B  T D>?o   0e0e    BvCWDE F Ԕ 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||WvW@#f     <z##jJ"` j :  G Registers 0 B  !  3 r\~1?"`   ; RA0   "  3 r1?"`  7 :RB0   #  3 r1?"`I L  XBusA0  B $ T D1? :  %  3 r1?"` } Y  `RegWrite" 0    &  3 rl1?"`I L 6 XBusB0  B '  T Do?# B ( T Do?# B )  T Do?_   *  3 r1?"`    :RW0  ~B + B N D1?C `  ,  3 rt1?"`& M|  : 50   -  3 rH1?"`I L   XBusW0   .  3 rĝ1?"`n ; 320   /  T jJ?v;  0  # l(1?"` AAddress0 2 B 1  T D>?L67 2  # l1?"`64Y G Instruction 0( 2   3  # lP1?"`<Q LInstruction Memory0  B 4   ` D>?v#~B 5 B N DjJ?n 6  3 rح1?"`k ; 320  ~B 7 B N DjJ?2T 8  3 r1?"`- ; 300  ~B 9 B N DjJ?L,jT    : # 3L:  ;  TjJ"` `   <PC0B  <  TjJ"`  `  <000BB =  f D>?i6 >  3 rTjJ?"`/i E +1&0  ?  3 rp1?"`3O ; 300  ~B @ B N DjJ?3  A   0e0e    BC DEF > 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||W   @,6~B B B N D>?#f#s   C  3 r1?"`M  TRs0  ~B D B N D1?C `  E  3 r81?"`& m|  : 50   F  3 rX1?"`\U  :Rd0  T  oV  G #  h 2 H  T jJ? oV  I   fxaxa1?"` :  @Extender  P B~B J B N DjJ?& JC B K  T D1?   L  3 r1?"` *  ]ExtOp"0   M  3 rP1?"`y J =Imm160    N  3 r1?"`l  TRt0  T  jF  O # _ x" P  HG0*jJ? jF  Q B  `x1?"` jF  Am u x  Fc  R B  `1?"` wF  50 B  S B  `1?"` F  51 B ~B T B N D1?yU   U  3 r 1?"`\   : 50  " V  S 0e0e    BWCWDE F o 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||WWW@"`SB W T D1?% %   X  3 r1?"` Y  ^RegDst"0   Y  C x1?"` f ^ALUSrc"0  T  jF  Z #  oU x" [  HG0*jJ? jF  \ B  `1?"` jF  Am u x  Fc  ] B  ` 1?"` wF  50 B  ^ B  `@ 1?"` F  51 B B _ T D>?i ~B ` B N DjJ? I  a  3 r 1?"`  I ; 320   b   0e0e    BvCWDE F o 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||WvW@#: s B c B T D1?561  FL d # + ,$D  0 e  3 r1?"` F ]MemRead 0  B f  T D1?L2 FL g #  ,$D  0 h  3 r 1?"`F ^MemWrite 0   B i  T D1?L  J  j #   c ,$D 0T X   k #  l  3 r 1?"`X   ; 320  ~B m B N DjJ?  N  J  n   J  o  3 r 1?"`J D ALU result 0    N    p    B q  T D>?,6/6T    r # JS~B s B N DjJ?Y   t  3 r 1?"` Y  ; 320  T  jF  u # 0px" v  HG0*jJ? jF  w B  `D# 1?"` jF  Am u x  Fc  x B  `\' 1?"` wF  50 B  y B  `+ 1?"` F  51 B 2 z  S 0e0e    BcCDEF > 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||<c< @"`0  {   0e0e    B= CzDEF > 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E|| = = zz @  4 3 | # ,$D 0B }  T D1?ii ~  3 r/ 1?"`3 `MemtoReg" 0     ND4 jJ? 7X p ,$D 0 ^"ALU calculates data memory address #0( 2#H  0޽h ? a(((___PPT10(.P+D{'' Z= @B D6'' = @BA?%,( < +O%,( < +D' =%(D' =%(D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* D' =%(D' =%(D@' =A@BB BB0B%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* D' =%(D' =%(D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* D' =%(D' =%(D@' =A@BB BB0B%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* D' =%(D' =%(D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<*j %(D' =-o6Bdissolve*<3<*j D' =%(D' =%(D@' =A@BB BB0B%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* D' =%(D' =%(D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<*  %(D' =-o6Bdissolve*<3<*  Ds' =%(D' =%(D@' =A@BB BB0B%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* D@' =A@BB BB0B%(D' =1:Bvisible*o3>+B#style.visibility<* 9%(D' =-o6Bdissolve*<3<* 9D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<*d %(D' =-o6Bdissolve*<3<*d D+' =%(D' =%(D@' =A@BB BB0B%(D' =1:Bvisible*o3>+B#style.visibility<* 9Y%(D' =-o6Bdissolve*<3<* 9YD3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<*g %(D' =-o6Bdissolve*<3<*g D+' =%(D' =%(D@' =A@BB BB0B%(D' =1:Bvisible*o3>+B#style.visibility<* Y%(D' =-o6Bdissolve*<3<* YD3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<*| %(D' =-o6Bdissolve*<3<*| ++0+ 0 ++0+ 0 ++0+ 0 ++0+ 0 +ȣ  0 >y6y! x(     NO jJ? T $,$@ 0 ALUCtrl =  ADD to calculate data memory address as Reg(Rs) + sign-extend(Imm16) Q0( 2Q$-~  NlS jJ? T c ,$@ 0 vALUSrc =  1 selects extended immediate as second ALU input <0( 2<6~  s *$X  `   J  N8Y jJ? / Y ,$@  0 BMemRead =  1 to read data memory "0( 2"x  N8^ jJ?& T ,$@ 0 ^RegDst =  0 selects Rt as destination register 00( 20$   `c jJ?"` y,$@ 0 jExtOp =  sign to sign-extend Immmediate16 to 32 bits 60( 261  Ni jJ? / Y$,$@ 0 |RegWrite =  1 to write the memory data on BusW to register Rt ?0( 2?6#   N|n jJ? / Yd ,$@  0 nMemtoReg =  1 places the data read from memory on BusW 80( 28$+   0e0e    BvCWDE F o 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||WvW@S" : ;s   <s ##jJ"`M!s  G Data Memory 0 B   3 r|x 1?"`m! @ Address 0     C x| 1?"`R<F  YData_in0     3 r 1?"` \Data_out 0   |B  T Df>?66L V #   # f~B  B N DjJ?     3 r 1?"`V #  ; 320  L     # $S~B  B N DjJ?Y     3 r8 1?"` Y  ; 320  "  c BC DE F*jJ? p ` @`S" 1     f xaxa1?"` =A L U PB9   #  M,$D  0B   T Do?   3 r` 1?"` e ALUCtrl = ADD"0    3 r 1?"`J D ALU result 0     3 rЛ 1?"`1~  ; 320  vB  @ N DjJ? L X   ! # b "  3 rt 1?"`X   ; 320  ~B # B N DjJ?  |B $ T D>?u |B % T Df>?S  &  0e0e    BvCWDE Ff Ԕ 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||WvW@S" f ' <D ##jJ"`v :  G Registers 0 B  ( 3 r 1?"`  ; RA0   ) 3 r 1?"`  7 :RB0   * 3 rD 1?"`k Z  XBusA0  >  : f  + # : G ,$D 0B , T D1? :  " -  C x 1?"` f  d RegWrite = 1" 0    . 3 r 1?"`k Z 6 XBusB0  |B / T Dfo?|B 0 T Do?|B 1 T Dfo? 2 3 r 1?"`    :RW0  vB 3 @ N D1? 4 3 rH 1?"`Mr : 50   5 3 r` 1?"`k Z   XBusW0   6 3 r 1?"`hn ; 320  | 7 T jJ?e;  8 # lp 1?"`) AAddress0 2 |B 9 T Df>?6 e7 : # lh 1?"`4 G Instruction 0( 2   ; # l` 1?"`Q LInstruction Memory0  B <  ` Df>?vB = @ N DjJ?n3 > 3 rX 1?"` ; 320  vB ? @ N DjJ?T @ 3 r 1?"`k ; 300  vB A @ N DjJ?LjL    B # 3 :  C  T jJ"` `   <PC0B  D  T jJ"`  `  <000BB E  f Df>?i[[6 F 3 rx jJ?"`i E +1&0  G 3 r 1?"`wO ; 300  vB H @ N DjJ?Bv3 I  0e0e    BC DEFf > 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||W   @S" ,[6vB J @ N Df>?fs  K 3 r 1?"`MW TRs0  vB L @ N D1? M 3 r 1?"`mr : 50   N 3 r#1?"`"U  :Rd0  |2 O T fjJ?t  P  f #xaxa1?"`t  DExtender  P FfvB Q @ N DjJ?Jr8    R #  ,$D 0B S  T D1?   T  3 rd #1?"`   d ExtOp = sign" 0    U 3 rX 1?"`J =Imm160   V 3 r|#1?"`lW TRt0  L  jF  W # < x" X  HG0*jJ? jF  Y B  `t#1?"` jF  Am u x  Fc  Z B  `#1?"` wF  50 B  [ B  `8#1?"` F  51 B vB \ @ N D1?U   ] 3 rt!#1?"`   : 50   ^  0e0e    BWCWDE Ff o 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||WWW@c"$` <SL  jF  _ #  S U x" `  HG0*jJ? jF  a B  `%#1?"` jF  Am u x  Fc  b B  `\)#1?"` wF  50 B  c B  `-#1?"` F  51 B L  jF  d # ox" e  HG0*jJ? jF  f B  `<1#1?"` jF  Am u x  Fc  g B  `4#1?"` wF  50 B  h B  `8#1?"` F  51 B |B i T Df>?u vB j @ N DjJ?I  k 3 r =#1?"`  I ; 320  $ l  0e0e    BcCDEF > 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||<c< @c"$` , m  0e0e    BCDEF  > 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||   @c"$`  ! =   }L n #  L,$D  0! o  C xB#1?"`  } c MemRead = 1" 0   B p  T D1?L8  L q #  L,$D  0 r  3 rpG#1?"`  d MemWrite = 0" 0   B s  T D1?L t  0e0e    B= CzDEFf > 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E|| = = zz @S"  c  S  u # S ,$D 0B v T D1?% %    w  C xL#1?"`  b RegDst = 0" 0   ~B x  N Dfo?S` vB y N Dfo?|B z T Df>?!     { #   ,$D 0 N   |     }  C xR#1?"` f b ALUSrc = 1" 0   B ~ B T D1?56~B  B N Df>? p " 36  #  ~6,$D 0 N 3   3B   T D1?ii"   C xX#1?"`3 d MemtoReg = 1" 0   ~B  B N Df>?06   0e0e    BCDEFf > 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E|| @S" fu  L #Z    #  f ~B  B N DjJ?A ^    3 r]#1?"`#Z   ; 320  H  0޽h ? a(2***___PPT10 *.P+D.DV(' Z= @B D(' = @BA?%,( < +O%,( < +D+' =%(D' =%(D@' =A@BB BB0B%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<*u %(D' =-o6Bdissolve*<3<*u D+' =%(D' =%(D@' =A@BB BB0B%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<*R %(D' =-o6Bdissolve*<3<*R D+' =%(D' =%(D@' =A@BB BB0B%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<*{ %(D' =-o6Bdissolve*<3<*{ D+' =%(D' =%(D@' =A@BB BB0B%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* D+' =%(D' =%(D@' =A@BB BB0B%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<*n %(D' =-o6Bdissolve*<3<*n D' =%(D' =%(D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<*q %(D' =-o6Bdissolve*<3<*q D+' =%(D' =%(D@' =A@BB BB0B%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* D+' =%(D' =%(D@' =A@BB BB0B%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<*+ %(D' =-o6Bdissolve*<3<*+ ++0+ 0 ++0+ 0 ++0+ 0 ++0+ 0 ++0+ 0 ++0+ 0 ++0+ 0 +  0 `wXw! v(      0e0e    B= CzDEF > 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E|| = = zz @S"  c |B  T D>?66  Nl|#jJ? = ,,$@ 0 ALUCtrl =  ADD to calculate data memory address as Reg(Rs) + sign-extend(Imm16) Q0( 2Q$-  N#jJ? = c ,$@ 0 ALUSrc =  1 to select the extended immediate as second ALU input B0( 2B<~  s *؆# `  # N  Nć#jJ? /  ,$@  0 FMemWrite =  1 to write data memory $0( 2$`  ND#jJ?& = ,$@ 0 XRegDst =  x because no destination register -0( 2-'    `\#jJ?"` =y,$@ 0 jExtOp =  sign to sign-extend Immmediate16 to 32 bits 60( 261   N$#jJ? / ,,$@ 0 RegWrite =  0 because no register is written by the store instruction G0( 2G?   N4#jJ? / d ,$@  0 MemtoReg =  x because we don t care what data is placed on BusW A0( 2A$4    0e0e    BvCWDE F o 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||WvW@S" : ;s    <###jJ"`M!s  G Data Memory 0 B   3 r#1?"`m! @ Address 0      3 rP#1?"`R<t  YData_in0     3 r#1?"` \Data_out 0   L V #   # f~B  B N DjJ?     3 r#1?"`V #  ; 320  L #Z    #  f ~B  B N DjJ?A ^    3 r@#1?"`#Z   ; 320  L     # $S~B  B N DjJ?Y     3 r#1?"` Y  ; 320  "  c BC DE F*jJ? p ` @`S" 1     f#xaxa1?"` =A L U PB9   #  M,$D  0B   T Do?   3 r#1?"` e ALUCtrl = ADD"0    3 rt#1?"`J D ALU result 0      3 r#1?"`1~  ; 320  vB ! @ N DjJ? L X   " # b #  3 r#1?"`X   ; 320  ~B $ B N DjJ?  |B % T D>?u |B & T Df>?S  '  0e0e    BvCWDE Ff Ԕ 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||WvW@S" f ( <d###jJ"`v :  G Registers 0 B  ) 3 r #1?"`  ; RA0   * 3 r#1?"`  7 :RB0   + 3 rP#1?"`k Z  XBusA0  >  : f  , # : G ,$D 0B - T D1? :  " .  C x#1?"` f  d RegWrite = 0" 0    / 3 r#1?"`k Z 6 XBusB0  |B 0 T Dfo?|B 1 T Do? 2 3 r#1?"`    :RW0  vB 3 @ N D1? 4 3 r$#1?"`Mr : 50   5 3 r`#1?"`k Z   XBusW0   6 3 r#1?"`hn ; 320  | 7 T jJ?e;  8 # l%1?"`) AAddress0 2 |B 9 T Df>?6 e7 : # l%1?"`4 G Instruction 0( 2   ; # l%1?"`Q LInstruction Memory0  B <  ` Df>?vB = @ N DjJ?n3 > 3 r#1?"` ; 320  vB ? @ N DjJ?T @ 3 r%1?"`k ; 300  vB A @ N DjJ?LjL    B # 3 :  C  T%jJ"` `   <PC0B  D  T%jJ"`  `  <000BB E  f Df>?i[[6 F 3 r%jJ?"`i E +1&0  G 3 r( %1?"`wO ; 300  vB H @ N DjJ?Bv3 I  0e0e    BC DEFf > 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||W   @S" ,[6vB J @ N Df>?fs  K 3 r$%1?"`MW TRs0  vB L @ N D1? M 3 r(%1?"`mr : 50   N 3 rx-%1?"`"U  :Rd0  |2 O T fjJ?t  P  f1%xaxa1?"`t  DExtender  P FfvB Q @ N DjJ?Jr8    R #  ,$D 0B S  T D1?   T  3 r 6%1?"`   d ExtOp = sign" 0    U 3 r:%1?"`J =Imm160   V 3 r=%1?"`lW TRt0  L  jF  W # < x" X  HG0*jJ? jF  Y B  `B%1?"` jF  Am u x  Fc  Z B  `E%1?"` wF  50 B  [ B  `I%1?"` F  51 B vB \ @ N D1?U   ] 3 rM%1?"`   : 50   ^  0e0e    BWCWDE F o 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||WWW@c"$` <S6   _ #   ,$D 0B ` T D1?% %   a  3 rQ%1?"`  b RegDst = x" 0   L  jF  b #  S U x" c  HG0*jJ? jF  d B  `V%1?"` jF  Am u x  Fc  e B  `Y%1?"` wF  50 B  f B  `H^%1?"` F  51 B L  jF  g # ox" h  HG0*jJ? jF  i B  `b%1?"` jF  Am u x  Fc  j B  `f%1?"` wF  50 B  k B  `i%1?"` F  51 B |B l T Df>?u vB m @ N DjJ?I  n 3 rm%1?"`  I ; 320  $ o  0e0e    BcCDEF > 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||<c< @c"$` , p  0e0e    BCDEF f > 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||   @c"$`  ! =   }L q #  L,$D  0! r  C x8r%1?"`  } c MemRead = 0" 0   B s  T D1?L8  L t #  L,$D  0 u  3 rw%1?"`  d MemWrite = 1" 0   B v  T D1?L> 3 w #  ~,$D 0B x  T D1?ii" y  C x|%1?"`3 d MemtoReg = x" 0   |B z T Df>?!    { #   ,$D 0  |  C x%1?"` f b ALUSrc = 1" 0   B } B T D1?56~B ~ B N Df>? p |B  T Dfo?vB  N Df>?v    0e0e    BCDEFf > 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E|| @S" fu  H  0޽h ? a(2***___PPT10 *.P+|DV(' Z= @B D(' = @BA?%,( < +O%,( < +D+' =%(D' =%(D@' =A@BB BB0B%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<*_ %(D' =-o6Bdissolve*<3<*_ D+' =%(D' =%(D@' =A@BB BB0B%(D' =1:Bvisible*o3>+B#style.visibility<*  %(D' =-o6Bdissolve*<3<*  D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<*R %(D' =-o6Bdissolve*<3<*R D+' =%(D' =%(D@' =A@BB BB0B%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<*{ %(D' =-o6Bdissolve*<3<*{ D+' =%(D' =%(D@' =A@BB BB0B%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* D' =%(D' =%(D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<*q %(D' =-o6Bdissolve*<3<*q D+' =%(D' =%(D@' =A@BB BB0B%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<*t %(D' =-o6Bdissolve*<3<*t D+' =%(D' =%(D@' =A@BB BB0B%(D' =1:Bvisible*o3>+B#style.visibility<*  %(D' =-o6Bdissolve*<3<*  D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<*w %(D' =-o6Bdissolve*<3<*w D+' =%(D' =%(D@' =A@BB BB0B%(D' =1:Bvisible*o3>+B#style.visibility<*  %(D' =-o6Bdissolve*<3<*  D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<*, %(D' =-o6Bdissolve*<3<*, ++0+ 0 ++0+ 0 ++0+ 0 ++0+ 0 ++0+  0 ++0+  0 ++0+  0 +  0 JwBw`$ 0 v(   r  S % `  %    6%"` 6K<$ 0 % L  oV  H #  2 I  T jJ? oV  J   f\%xaxa1?"` :  ;Ext PB B " Z D>?Pw PB e Z D>?y y  B%##jJ"`(?  G Data Memory 0 B   C x`%1?"`9 @ Address 0     C xP%1?"` YData_in0  B  Z D>?&  C x%1?"`} Y \Data_out 0   B  Z D>?'L bP  # Cw   3 r%1?"`bP ]MemRead 0     3 r%1?"`LP ^MemWrite 0   L     # rB~B  B N DjJ?Y     3 r%1?"` Y  ; 320  "  c BC DE F*jJ? p ` @`S" &  # l%xaxa1?"`H&^ =A L U PB  C x%1?"`p S  _ALUCtrl"0    C x8%1?"` D ALU result 0   L X    #    3 r%1?"`X   ; 320  ~B  B N DjJ?  B ! Z D>?   #  0e0e    BvCWDE F > 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||WvW@2z $ B%##jJ"`;   G Registers 0 B  % C x%1?"`S; E  ; RA0   & C xP%1?"`UV E  :RB0   ' C x%1?"`A  XBusA0  B ( Z D1? * +  ) C x,1?"` o ^  `RegWrite" 0    * C x,1?"`  XBusB0  B + Z Do?; B , Z Do?: B - Z Do?6  . C xl ,1?"`sV E  :RW0  |B / @ T D1?o 0 C x ,1?"` o : 50   1 C x|,1?"`v  XBusW0   2 C x,1?"`C: ; 320   3 Z jJ?'  4 3 r,1?"`mY AAddress0 2 B 5 Z D>?   6 3 r,1?"`  G Instruction 0( 2   7 3 r",1?"` LInstruction Memory0  B 8  f D>?V'V|B 9 @ T DjJ?:]wtL    < # P  =  T',jJ"` `   <PC0B  >  T4%,jJ"`  `  <000BB ? # l D>?0  @ C x.,jJ?"`On5 = +10 L PJ  # ) A  3 r3,1?"`PJ ; 300  ~B B B N DjJ?|B C @ T D>?2?   D C x7,1?"`1o TRs0  |B E @ T D1? F C x;,1?"`9  : 50   G C x?,1?"`f!  :Rd0  |B K @ T DjJ?@ [ P M C xxC,1?"`  =Imm260    N C xG,1?"`81 TRt0  L  jF  O # x x" P  HG0*jJ? jF  Q B  `K,1?"` jF  Am u x  Fc  R B  `O,1?"` wF  50 B  S B  `HS,1?"` F  51 B |B T @ T D1?! 1[  U C xW,1?"`\ K  : 50   V S 0e0e    BWCWDE F o 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||WWW@"`0B W Z D1?x   X C xP[,1?"` ,6 ^  ^RegDst"0   Y C x_,1?"`p  ^ALUSrc"0  L  jF  Z #  w ! x" [  HG0*jJ? jF  \ B  `c,1?"` jF  Am u x  Fc  ] B  `tg,1?"` wF  50 B  ^ B  `k,1?"` F  51 B L  jF  _ # ;x" `  HG0*jJ? jF  a B  `To,1?"` jF  Am u x  Fc  b B  `ls,1?"` wF  50 B  c B  `pq,1?"` F  51 B * h S 0e0e    BcCDEF > 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||<c< @"`  i  0e0e    BvCWDE F o 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||WvW@ ? 2 j S 0e0e    BCDEF  > 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||   @"` y lL C- k # B l  T D1?CCB m  T D1?-- n  0e0e    B= CzDEF > 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E|| = = zz @r4  B o Z D1?lKK p C xD|,1?"`}M `MemtoReg" 0   B t Z Do?p  v S 0e0e    B] CDE F > 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||] @"`SNL  jF  w # @dx" x  HG0*jJ? jF  y B  `,1?"` jF  Am u x  Fc  z B  `8,1?"` wF  51 B  { B  `,1?"` F  50 B B } Z D1?! I I ^ L ~ f   #  j   3 r`,1?"`~ f  ; 300  ~B  B N DjJ?  |B  @ T DjJ?P l jF  jF,$D 0`B  0DF   C xܑ,1?"`j0 Bzero"0  L lF  # Uq   3 r@,1?"`l ; 300  ~B  B N DjJ? 3F   C x,1?"`8 UJump or Branch Target Address0  ^B  6D> G L ~ f   # Uj   3 r,1?"`~ f  ; 300  ~B  B N DjJ?     BdC1DEFAA>d11 @"`S  S B C#DEFAA> ## @"`ZT}l  C@   C@,$D  0   C B CuDEFA D u @S" C@   C x,1?"` c ]PCSrc"0    c BCkDE FAA>kk@g  pB  HDԔ6g g   C x,1?"`  =Imm160  l &S]   S&] ,$D 0   C BqC3DE FAq3q@S" &Sj`B  B 0D&`B  B 0D&66;   C x,1?"`=t ]  } J, Beq, Bne" 0   ,`B   0DoSp   C x,jJ?"`& CNext PC 0 xB  Z,jJ?"`E Y| ,$@ 0 v:Next PC computes jump or branch target instruction address ;0( 2;$  T ,jJ?"` YB,$D  0 ^"For Branch, ALU does a subtraction #0( 2#H  0޽h ? 33___PPT10.+OXD' ,= @B D}' = @BA?%,( < +O%,( < +D+' =%(D' =%(D@' =A@BB BB0B%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* D3' =A@BBBB0B%(D' =?B70, 0; .2, .5; .8, .5; 1, 0-g6B fade*<3<* D' =0l9 BBBB*<3<* )?D' =%(D' =%(D@' =A@BB BB0B%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* D+' =%(D' =%(D@' =A@BB BB0B%(D' =1:Bvisible*o3>+B#style.visibility<* H%(D' =-o6Bdissolve*<3<* HD3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* D+' =%(D' =%(D@' =A@BB BB0B%(D' =1:Bvisible*o3>+B#style.visibility<* Hn%(D' =-o6Bdissolve*<3<* HnD3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* D+' =%(D' =%(D@' =A@BB BB0B%(D' =1:Bvisible*o3>+B#style.visibility<* n%(D' =-o6Bdissolve*<3<* nD3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* D' =%(D' =%(D@' =A@BB BB0B%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* ++0+ 0 ++0+ 0 ++0+ 0 ++0+ 0 +(  0 ''p$:C O'(   x  c $<, `  , pB  HD1yy\   c B=CPDE F>P=P=@ oyL `  # L *   c BC DE F*jJ? p ` @`S" `    f,xaxa1?"` ?A D D nBj  BjJ ^B  6D> s ^B  6D>?sL ?XB  @ 0DjJ;hl  T,"` 630(2 L  o R   #  {`B   0D> %  % ZB  B s *DjJ9 f R    N,"` o  630(2 L 0 =   #  x"   HG0*1?0 =   B  `,1?"`0 =  w 0 m u x 1N F0 F( F0 F(c  T<,"`i/ 6Inc PC 2XB  @ 0DjJ1;h  Tx,"` 630(2    BCDE F>@"`_L   T,"`   9Imm16(2  T,"` iE  5Imm26 2XB  @ 0DjJB    T-"` _ + 630(2 L     # B$ l"   <G0*jJ     N-"`   6SE(2   BCDE FjJ@"`> 4 XB ! @ 0D1 > k b  " T -"`   54(2  # T -"` E )   Qmsb(2 XB $ @ 0DjJb > k  % T-"` E  626(2 pB & HDԔ$  jr ' B1jr ( B1p ) HZG[D1 * @ c BDCDEF1DDrr @S"  + c BDCDEF1DDrr @c"$` [d2 , <1j -  BqCqDE F1qqq@S"  O [  .  BqCqDE F1qqq@S"   /  BqCqDE F1qqq@S" Y 0 @  BqCqDE F1qqq@c"$` ; 1 T|-"`{ SBeq(2 2 T,"` |6  SBne(2 3 T-"` |  7J(2 4 T#-"` p   :Zero(2^B : 6D1;=  ; Tl(-"` UPCSrc(2 < T@--"`"_  MBranch or Jump Target Address 2^B = 6D1yy ? Tx"- "` kYY - LB @ c $D` # ` C 61-jJ=8  b2Sign-Extension: Most-significant bit is replicated3 23H  0޽h ? 33___PPT10i.:+D=' \= @B +  0 ˂Â$ O(    j c BCkDE F>kk@S" ~  pB k HDԔ6v v B  Z D>?' T  0e0e    BvCWDE F o 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||WvW@S"  ? B 4 # l D>?0  h  BdC1DEF>d11 @c"$` Sr  S  `      0e0e    B= CzDEF > 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E|| = = zz @S" r  L  oV   # # 2   T jJ? oV     f@-xaxa1?"` :  ;Ext PB B  Z D>?Pw PB  Z D>?fW f  B$F-##jJ"`(?  G Data Memory 0 B   C xJ-1?"`9 @ Address 0     C xTN-1?"` YData_in0  B  Z D>?&  C xQ-1?"`} Y \Data_out 0   L     # rB~B  B N DjJ?Y     3 r V-1?"` Y  ; 320    C xpZ-1?"` D ALU result 0   L X    #    3 r^-1?"`X   ; 320  ~B  B N DjJ?  B  Z D>?m     0e0e    BvCWDE Ff > 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||WvW@S" )B  Z Do?; B  Z Do?: B  Z Do?6 |B  @ T D1?o  C xd-1?"` o : 50  \L ;    ! # ; m   "  <|h-##jJ"`;    G Registers 0 B  #  3 rk-1?"`; SE  ; RA0   $  3 rp-1?"`V UE  :RB0   %  3 rm-1?"` A  XBusA0   &  3 rw-1?"`   XBusB0   '  3 r y-1?"`V sE  :RW0   (  3 r-1?"` v  XBusW0   ) C x-1?"`C: ; 320   * Z jJ?'  + 3 r܇-1?"`mY AAddress0 2 B , Z Df>?   - 3 r-1?"`  G Instruction 0( 2   . 3 r0-1?"` LInstruction Memory0  B /  f Df>?V'V|B 0 @ T DjJ?:]wtL    1 # P  2  Tԓ-jJ"` `   <PC0B  3  T8-jJ"`  `  <000BL PJ 6 # ) 7  3 rP-1?"`PJ ; 300  ~B 8 B N DjJ?|B 9 T Df>?)%   : C x-1?"`1o TRs0  |B ; @ T D1? < C x-1?"`9  : 50   = C x -1?"`f!  :Rd0  |B > @ T DjJ?@ [ L ? C xH-1?"`  =Imm260    @ C x-1?"`81 TRt0  L  jF  A # x x" B  HG0*jJ? jF  C B  `0-1?"` jF  Am u x  Fc  D B  `ܸ-1?"` wF  50 B  E B  `@-1?"` F  51 B |B F @ T D1?! 1[  G C x-1?"`\ K  : 50   H  0e0e    BWCWDE F o 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||WWW@c"$` 0L  jF  I #  w ! x" J  HG0*jJ? jF  K B  `-1?"` jF  Am u x  Fc  L B  `-1?"` wF  50 B  M B  `P-1?"` F  51 B L  jF  N # ;x" O  HG0*jJ? jF  P B  `-1?"` jF  Am u x  Fc  Q B  `8-1?"` wF  50 B  R B  `0-1?"` F  51 B $ S  0e0e    BcCDEF > 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||<c< @c"$`  , U  0e0e    BCDEF  > 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||   @c"$`  y  V  0e0e    B] CDE F > 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||] @c"$` SNL  jF  W # @dx" X  HG0*jJ? jF  Y B  `P-1?"` jF  Am u x  Fc  Z B  `-1?"` wF  51 B  [ B  ``-1?"` F  50 B L ~ f  \ #  j ]  3 r-1?"`~ f  ; 300  ~B ^ B N DjJ?  |B _ @ T DjJ?_ L lF ` # Uq a  3 r-1?"`l ; 300  ~B b B N DjJ? 3F5 c C xT-1?"`8,$ 0 KJump Target Address0  L ~ f  e # Uj f  3 r-1?"`~ f  ; 300  ~B g B N DjJ?   i S B C#DEFf> ## @c"$` ZTp l C x-1?"`  =Imm160   m C x/jJ?"`& CNext PC 0 xl o w   o w ,$D  0B r T D1?* +  s  3 r/1?"`o  d RegWrite = 0" 0   o@ Cw   Cw T bP n # Cw o  3 r /1?"`bP c MemRead = 0" 0    p  3 r$/1?"`LP d MemWrite = 0" 0   tT C- w #  B x  T D1?CCB y  T D1?--l &F   F& ,$@ 0   C BqC3DE Fq3q@S" &F]ZB  B s *D&ZB  B s *D&))   3 r/1?"`=z   CJ = 1"0  ZB   s *DoFc 0 l ,/   ,/ ,$D  0@ ,} 6   ,} 6 B t T D1?}   u  3 r/1?"`, 6  b RegDst = x" 0   @  /    /  q  3 r-1?"` z S/  c ALUCtrl = x" 0    v  3 r/1?"` z /  b ALUSrc = x" 0   B z  T D1?II {  3 r$/1?"`}m d MemtoReg = x" 0   B | T Do?c B } T D1?I  I Q Y@  2P /    2P /    # B[C1DE FA[1@S"  2# c    3 r)/1?"` z P /  a ExtOp = x" 0   l Cp  Cp,$D 0m@  C3   C3 ~  C B CuDEF D u @S" C3   3 r./1?"`  a PCSrc = 1" 0      S BTC[DEFf>[q[T @S" Gp 5 C x`3/jJ?"`On5 = +10 F jF   jFZB  s *DF   3 r7/1?"`j0 Bzero"0  i8 &  &*   c BC DE F*jJ? p ` @`S" &   # lCkDEFAf>k[k>D> @S"  ),$@ 0XB  0Df>GH  0޽h ? 33___PPT10.adj+=DM' \= @B D' = @BA?%,( < +O%,( < +D ' =%(DV ' =%(D@' =A@BB BB0B%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* D@' =A@BB BB0B%(D' =1:Bvisible*o3>+B#style.visibility<*c %(D' =-o6Bdissolve*<3<*c D' =%(D' =%(D@' =A@BB BB0B%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* D+' =%(D' =%(D@' =A@BB BB0B%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* D+' =%(D' =%(D@' =A@BB BB0B%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* D+' =%(D' =%(D@' =A@BB BB0B%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* +P+0+c 0 ++0+ 0 ++0+ 0 ++0+ 0 ++0+ 0 ++0+ 0 +>  0 $ 0 (    d c BCkDE F>kk@S" ~  jB e BDԔ6v v  E  0e0e    BWCWDE F o 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||WWW@c"$` 0|B  T D>?'   0e0e    BvCWDE F o 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||WvW@S"  ? B   f Df>?0    BdC1DEF>d11 @c"$` Sx  c $t/ `  /    0e0e    B= CzDEF > 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E|| = = zz @S" r  L  oV   # # 2   T jJ? oV     fv/xaxa1?"` :  ;Ext PB |B  T Df>?Pw P|B  T Df>?fW f  <~/##jJ"`(?  G Data Memory 0 B   3 rā/1?"`9 @ Address 0      3 rT/1?"` YData_in0  |B  T D>?&   3 r/1?"`} Y \Data_out 0   L     # rB~B  B N DjJ?Y     3 rج,1?"` Y  ; 320    3 r/1?"` D ALU result 0   L X    #    3 r$/1?"`X   ; 320  ~B  B N DjJ?     0e0e    BvCWDE Ff > 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||WvW@S" )|B  T Dfo?; |B  T Dfo?: |B  T Do?6 vB  @ N D1?o  3 rȚ/1?"` o : 50  \L ;     # ; m   !  <X/##jJ"`;    G Registers 0 B  "  3 r/1?"`; SE  ; RA0   #  3 rl/1?"`V UE  :RB0   $  3 rԪ/1?"` A  XBusA0   %  3 rĮ/1?"`   XBusB0   &  3 rd/1?"`V sE  :RW0   '  3 r/1?"` v  XBusW0   ( 3 r/1?"`C: ; 320  | ) T jJ?'  * # lD/1?"`mY AAddress0 2 |B + T Df>?   , # l/1?"`  G Instruction 0( 2   - # lp/1?"` LInstruction Memory0  B .  ` Df>?V'VvB / @ N DjJ?:]wtL    0 # P  1  T/jJ"` `   <PC0B  2  T8/jJ"`  `  <000BL PJ 3 # ) 4  3 r/1?"`PJ ; 300  ~B 5 B N DjJ?vB 6 N Df>?)%  7 3 rX/1?"`1o TRs0  vB 8 @ N D1? 9 3 r/1?"`9  : 50   : 3 r@/1?"`f!  :Rd0  vB ; @ N DjJ?@ [ L < 3 rX/1?"`  =Imm260   = 3 r\/1?"`81 TRt0  L  jF  > # x x" ?  HG0*jJ? jF  @ B  `h/1?"` jF  Am u x  Fc  A B  `/1?"` wF  50 B  B B  `/1?"` F  51 B vB C @ N D1?! 1[  D 3 r/1?"`\ K  : 50  L  jF  F #  w ! x" G  HG0*jJ? jF  H B  `/1?"` jF  Am u x  Fc  I B  `|/1?"` wF  50 B  J B  `21?"` F  51 B L  jF  K # ;x" L  HG0*jJ? jF  M B  `021?"` jF  Am u x  Fc  N B  `, 21?"` wF  50 B  O B  `$ 21?"` F  51 B $ P  0e0e    BcCDEF > 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||<c< @c"$`  , Q  0e0e    BCDEF  > 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||   @c"$`  y  R  0e0e    B] CDE Ff > 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||] @c"$` SNL  jF  S # @dx" T  HG0*jJ? jF  U B  ``21?"` jF  Am u x  Fc  V B  `421?"` wF  51 B  W B  `21?"` F  50 B L ~ f  X #  j Y  3 r21?"`~ f  ; 300  ~B Z B N DjJ?  vB [ @ N DjJ?_ L lF \ # Uq ]  3 rP!21?"`l ; 300  ~B ^ B N DjJ? 3F1 _ 3 r%21?"`8,$ 0 MBranch Target Address0  L ~ f  ` # Uj a  3 r)21?"`~ f  ; 300  ~B b B N DjJ?   c S B C#DEFf> ## @c"$` ZTp f 3 r.21?"`  =Imm160   g 3 r12jJ?"`& CNext PC 0 xz o w  h  o w ,$D  0B i T D1?* +  j  3 r8621?"`o  d RegWrite = 0" 0   }N Cw  k  Cw T bP l # Cw m  3 rt:21?"`bP c MemRead = 0" 0    n  3 r>21?"`LP d MemWrite = 0" 0   tT C- o #  B p  T D1?CCB q  T D1?--l &FzF   F&zF ,$D 0 s  C BqC3DE Fq3q@S" &F]`B t B 0D&`B u B 0D&))7 v  C xD21?"`=c zF  yBeq = 1 Bne = 1"0  $`B w  0DoFc l  S/    S/ ,$@ 0# }  C xJ21?"` z S/  e ALUCtrl = SUB"0    ~  C xN21?"` z /  b ALUSrc = 0" 0   B  Z Do?c B  Z D1?I  I Q l ,/   ,/ ,$D 0 T ,} 6  y # ,} 6 B z T D1?}   {  3 r`T21?"`, 6  b RegDst = x" 0   B   Z D1?II"   C x\Y21?"`}m d MemtoReg = x" 0   sT  2P /   #  2P /    3 B[C1DE F[1@S"  2# c    3 r]21?"` z P /  a ExtOp = x" 0   z Cp   Cp,$D  0{N  C3    C3   C B CuDEF D u @S" C3   3 rxb21?"`  a PCSrc = 1" 0      S BTC[DEFf>[q[T @S" Gp  3 r|g2jJ?"`On5 = +10 z jF   jF,$D 0ZB  s *DF   3 rl21?"`j0 Bzero"0  qF &   &*   c BC DE F*jJ? p ` @`S" &    fp2xaxa1?"`H&^ =A L U PBg   `n2jJ?"`v YY,$@  0 RegDst = ExtOp = MemtoReg = x0( 26l   `8z2jJ?"`v' \,$@  0 "MemRead = MemWrite = RegWrite = 0 #0( 2#6T   `2jJ?"` '& ,$@ 0 Either Beq or Bne =10( 2,/   `\2jJ?"`s ' U ,$@ 0 ]%Next PC outputs branch target address&0 &XB  0Df>G|B  T Df>?m    Nԉ2jJ? ' 2,$@ 0 ALUSrc =  0 (2nd ALU input is BusB) ALUCtrl =  SUB produces zero flag.H0 76C  N2jJ? Y2,$@  0 5Next PC logic determines PCSrc according to zero flag60( 26H  0޽h ? 33\$T$___PPT104$.adj+ nD"' \= @B D;"' = @BA?%,( < +O%,( < +D+' =%(D' =%(D@' =A@BB BB0B%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* D8' =%(D' =%(D@' =A@BB BB0B%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* D@' =A@BB BB0B%(D' =1:Bvisible*o3>+B#style.visibility<*_ %(D' =-o6Bdissolve*<3<*_ Df' =%(D' =%(D@' =A@BB BB0B%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* D+' =%(D' =%(D@' =A@BB BB0B%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* D+' =%(D' =%(D@' =A@BB BB0B%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<*h %(D' =-o6Bdissolve*<3<*h D+' =%(D' =%(D@' =A@BB BB0B%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* ++0+_ 0 ++0+ 0 ++0+ 0 ++0+ 0 ++0+ 0 ++0+ 0 ++0+ 0 + ! 0L0 # <(   ~  s *2 `  2 ~  s *ȱ2 ` 2 H  0޽h ? X(=^___PPT10i.D`+D=' \= @B +.  0 --"4>$ @D-(  $ ~ $ s *T2 `  2  $  N2jJ S"  X ! 2 *H` $  `42gֳgֳjJ ? J C0 icInput: 6-bit function field from instruction ALUOp from main control Output: ALUCtrl signal for ALU>,-H`)8  &?  >$ & ? B $  Z Do?P Z T    $ # ]= " $  T jJ?   $   `C1?"`   I ALU Control" 0  T  c   $ # ^ = "  $  T jJ? c   $  T21?"` c  J Main Control" 0    $  Z21?"` B?I DDatapath 0( 2  "  $  Z jJ? &? $  C x<21?"`zd ; 320   $  Z jJ?}^ $  3 r21?"`I AAddress0 2  $  3 rH1?"`JC- G Instruction 0( 2   $  3 r21?"`0}) LInstruction Memory0  B $   ` D>?^B $ B T DjJ?B $  T D>?* $  c BC DE F*jJ? p ` @`S" " $  # ld2xaxa1?"`D'" =A L U PBB $ Z Do?/B $  # l Do?B $ Z D1? $  C xD21?"`3N QOp620   0 $  S ~31?"`h lRegDst00   B  $ Z D1?""2 !$  S ~031?"`W nRegWrite0 0   B "$ Z D1?/ #$  S ~P 31?"`r kExtOp00   B $$ Z D1?, , 0 %$  S ~p31?"`a  lALUSrc00   B &$ Z D1?  1 '$  S ~|31?"`|   mMemRead00   B ($ Z D1?6 6 2 )$  S ~31?"` Ik  nMemWrite0 0   B *$ Z D1?  2 +$  S ~31?"` ,  nMemtoReg0 0   B ,$ Z D1?@ @ - -$  S ~x#31?"` t  iBeq00   B .$ Z D1?  - /$  S ~(31?"`   iBne00    2$  C x-31?"` 9 C  ]ALUOp"0   3$  C x4231?"`l _ALUCtrl"0   4$   0e0e    B CDE F o 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E|| @S" S ] 5$  S ~p631?"`   Rfunct600   2 8$  Z jJ? 5 B <$ T D1?P P   =$  C x;31?"`   MJ00   H $ 0޽h ?8$  a(___PPT10i.R+D=' \= @B +  0 .&$ , (   x  c $C3 `  3 l  C@   C@,$D 0 {  C B CuDEF D u @S" C@ |  C xH31?"` c ]PCSrc"0  `8 T   T   a   0e0e    B= CzDEF > 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E|| = = zz @ r T  oV   # #  2   T jJ? oV     fL3xaxa1?"` :  ;Ext PB B  Z D>?w PPB  Z D>?W ff   BdQ3##jJ"`(?  G Data Memory 0 B    C xU31?"`9 @ Address 0      C xY31?"` YData_in0  B  Z D>?&   C x\31?"`} Y \Data_out 0   B   Z D>?'T     # Br~B  B N DjJ?Y     3 rLa31?"` Y  ; 320  *   c BC DE F*jJ? p ` @`S" &   # lde3xaxa1?"`H&^ =A L U PB   C xDj31?"` D ALU result 0   T X    #    3 r|m31?"`X   ; 320  ~B  B N DjJ?  B  Z D>?m     0e0e    BvCWDE F > 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||WvW@2zB '  Z Do?; B ( Z Do?: B )  Z Do?6 B + B T D1?o ,  C x(r31?"` o : 50  z@ ;     ; m     Bv3##jJ"`;    G Registers 0 B  !  C x {31?"`; SE  ; RA0   "  C x`~31?"`V UE  :RB0   #  C x,31?"` A  XBusA0   &  C xt31?"`   XBusB0   *  C x,31?"`V sE  :RW0   -  C x،31?"` v  XBusW0   .  C x31?"`C: ; 320   /  Z jJ?'  0  3 r31?"`mY AAddress0 2 B 1  Z D>?   2  3 rؘ31?"`  G Instruction 0( 2   3  3 rМ31?"` LInstruction Memory0  B 4   f D>?'VVB 5 B T DjJ?]:wtT    6 # P  7  T3jJ"` `   <PC0B  8  Tt3jJ"`  `  <000BB 9 # l D>?0  :  C x|3jJ?"`On5 = +10 T PJ ; # ) <  3 r31?"`PJ ; 300  ~B = B N DjJ?B >  T D>?2  ?  C x(31?"`1o TRs0  B @ B T D1? A  C xd31?"`9  : 50   B  C x\31?"`f!  :Rd0  B C B T DjJ?@ [ P D  C x31?"`   =Imm260   E  C xĺ31?"`18 TRt0  T  jF  F # x x" G  HG0*jJ? jF  H B  `31?"` jF  Am u x  Fc  I B  `\31?"` wF  50 B  J B  `31?"` F  51 B B K B T D1?! 1[  L  C x31?"`\ K  : 50  " M  S 0e0e    BWCWDE F o 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||WWW@"`0T  jF  Q #  w ! x" R  HG0*jJ? jF  S B  `$31?"` jF  Am u x  Fc  T B  ` 31?"` wF  50 B  U B  `31?"` F  51 B T  jF  V # ;x" W  HG0*jJ? jF  X B  `31?"` jF  Am u x  Fc  Y B  `X31?"` wF  50 B  Z B  `P31?"` F  51 B 2 [  S 0e0e    BcCDEF > 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||<c< @"`  \   0e0e    BvCWDE F o 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||WvW@ ? : ]  S 0e0e    BCDEF  > 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||   @"` y " e  S 0e0e    B] CDE F > 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||] @"`SNT  jF  f # d@x" g  HG0*jJ? jF  h B  `$31?"` jF  Am u x  Fc  i B  `31?"` wF  51 B  j B  `\31?"` F  50 B T ~ f  l #   j m  3 r31?"`~ f  ; 300  ~B n B N DjJ?  B o B T DjJ?_  T lF q # Uq r  3 rD51?"`l ; 300  ~B s B N DjJ? 3F t  C x51?"`tE UJump or Branch Target Address0  fB u  6D> G T ~ f  v # Uj w  3 r51?"`~ f  ; 300  ~B x B N DjJ?   y   BdC1DEF>d11 @"`S z  S B C#DEF> ## @"`TZ} }  c BCkDE F>kk@~  xB ~  HDԔv 6v    C x51?"`   =Imm160     C x5jJ?"`& CNext PC 0 x2 l t j2  t j2,$D 0T jF  #  j9`B  0DF p  C x51?"`j0 Bzero"0     c B*CDE FAo **@S" t m 2fB  6Do  T ]  M  #    Sc 2   T jJ?]  M    fx5xaxa1?"`]  BALU Ctrl   F   C x31? "` 6 C  _ALUCtrl"0     C xx 51? "` $  ]ALUOp"0     0e0e    B3CCDE F o 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E|| 33CC@c"$` ~     C x$51? "`$ s  \func"0  l ,S  S,,$D 0@ ,S  ,S`B  0D } `B  0D   }    C BCDE FA@S" ] % J  O  C x)51?"`,6 6  ^RegDst"0   P  C x`.51?"` 6  ^ALUSrc"0   %  C x251?"`o 6  `RegWrite" 0   n @ G S  G S   C BqC3DE Fq3q@S" &Sj`B  B 0D&`B  B 0D&66;   C x$751?"`\ } J, Beq, Bne" 0   ,`B   0DoS    0e0e    B3CCDE F 5% 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||33CC@S" CI`B  0D< `B  0D<  c  C x,=51?"`} }  `MemtoReg" 0      C xA51?"` }m  _MemRead"0     C xE51?"`M }  `MemWrite" 0   `B   0DԔG I   # BCaDEFAa @S" 0 2#    3 r(J51?"`@ 6 #  ]ExtOp"0  l - t ,   -t ,,$D 0T &   # j" t ,2   T jJ?&     fN5xaxa1?"`& .  F Main Control   F   0e0e    B3CCDE F o 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||33CC@c"$`  j2   3 rpS51?"`-   @Op"0  H  0޽h ? 33  ___PPT10 .+.D ' \= @B Dm ' = @BA?%,( < +O%,( < +D' =%(D' =%(D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* D' =%(D' =%(D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* D' =%(D' =%(D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* D' =%(D' =%(D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-o6Bdissolve*<3<* +0  0L0 //0"5<, w/(  , . 'Y <,  #">2 xs  r'Y ,   f4f5PP 1?"` 0YP o!16-bit immediate is sign-extended""x$$`` ,   fi5PP 1?"`0 P o!16-bit immediate is zero-extended""x$$`` ,   f y5PP 1?"`'0P qExtOpx$$`` ,   fs5PP 1?"` YB  \Data memory is read Data_out ! Memory[address]/ /,x$$`` ,   f5PP 1?"` B  RNonex$$`` ,   f85PP 1?"`'B  sMemReadx$$``  ,   f@5PP 1?"` B Y  `Data memory is written Memory[address] ! Data_in1 1,x$$``  ,   f5PP 1?"`B  RNonex$$``   ,   fl5PP 1?"`'B   tMemWrite  x$$``A  ,   f$5PP 1?"` Y  BusW = Data_out from Memory$ x$$``%  ,   f5PP 1?"`  yBusW = ALU resultx$$``  ,   f5PP 1?"`'   tMemtoReg  x$$``V ,   f5PP 1?"` Y ZPC ! Branch target address If branch is taken. .x$$`` ,   fH5PP 1?"`  dPC ! PC + 4  x$$``2 ,   f45PP 1?"`'  Beq, Bne  $x$$``5 ,   f<5PP 1?"` PY ;Second ALU operand comes from the extended 16-bit immediate<<x$$``` ,   f6PP 1?"`P  DSecond ALU operand comes from the second register file output (BusB)EE?x$$`` ,   fl5PP 1?"`'P rALUSrcx$$``W ,   f6PP 1?"` Y0 ;Destination register is written with the data value on BusW<<7x$$`` ,   f6PP 1?"` 0 RNonex$$``  ,   f)6PP 1?"`'0 tRegWrite  x$$`` ,   f26PP1? Y ~0PC ! Jump target addressx$$`` ,   f-6PP1?  dPC ! PC + 4  x$$`` ,   fdE6PP1?' SJx$$``; ,   fDG6PP1?Y MThis multi-bit signal specifies the ALU operation as a function of the opcodeN Nx$$`` ,   fDX6PP1?' qALUOpx$$`` ,   fa6PP1? Y gDestination register = Rdx$$``' ,   fk6PP1?  Destination register = Rtx$$`` ,   ft6PP1?' rRegDstx$$``  ,  Z}61? Y pEffect when  1 x$$`` !,  Z61?  pEffect when  0 x$$`` ",  Z61?' XSignalx$$``xB #,  H 1 ?'YrB $,  B 1 ?'YxB %,  H 1 ?'YxB &,  H 1 ?''rB ',  B 1 ?rB (,  B 1 ?  xB ),  H 1 ?YYxB *,  H 1 ?'YrB +,  B 1 ?rB ,,  B 1 ?  rB -,  B 1 ?'YrB .,  B 1 ?'0Y0rB /,  B 1 ?'YrB 0,  B 1 ?'YrB 1,  B 1 ?' Y rB 2,  B 1 ?' Y rB 3,  B 1 ?'B YB rB 4,  B 1 ?'PYP~ 5, s *6 `  6 H , 0޽h ? a(y___PPT10Y+D=' \= @B +  0L0 ħP" 5 T(  4 h ' Y   5  #"B6 rrr"'Y  6 5   `6(k(k 1?"`   Q1x$$`` 5   `l6(k(k 1?"`   Q0x$$`` 4   `6(k(k1?I   Q0x$$`` 4   `p6(k(k1?v I  Q0x$$`` 4   `46(k(k1? v  Q0x$$`` 4   `6(k(k 1?"`  Q0x$$`` 4   `P6(k(k 1?"` Q0x$$`` 4   `6(k(k1?* Q0x$$`` 4   `P6(k(k 1?"`W* Q0x$$`` 4   `D8(k(k 1?"`W Q0x$$`` 4   ` 8(k(k1? Q0x$$`` 4  3 r 8(k0e(k0e1?"`  WJ(x$$`` 4   `H8(k(k 1?"`G  Qxx$$`` 4   `(%8(k(k 1?"`G   SSUBx$$`` 4   `-8(k(k 1?"`G I   SSUBx$$`` 4   `P78(k(k 1?"`G v I  SADDx$$`` 4   `(8(k(k 1?"`G v  SADDx$$`` 4   `H8(k(k 1?"`G   SXORx$$`` 4   `R8(k(k 1?"`G   RORx$$`` 4   `D8(k(k 1?"`G *  SANDx$$`` 4   `@d8(k(k 1?"`G W * SSLTx$$`` 4   `n8(k(k 1?"`G  W SADDx$$`` 4   `\_8(k(k 1?"`G   VR-typex$$`` 4  3 rPq8(k0e(k0e1?"`G   \ALU Op(x$$`` 4   `8(k(k 1?"` J  Q0x$$`` 4   `08(k(k 1?"`  J  Q0x$$`` 4   `8(k(k1? I J   Q1x$$`` 4   `ȣ8(k(k1? v J I  Q0x$$`` 4   `8(k(k1? J v  Q0x$$`` 4   `8(k(k 1?"` J  Q0x$$`` 4   ` 8(k(k 1?"` J  Q0x$$`` 4   `8(k(k1? *J  Q0x$$`` 4   `<8(k(k 1?"` WJ * Q0x$$`` 4   `x8(k(k 1?"` J W Q0x$$`` 4   `88(k(k1? J  Q0x$$``+ 4  3 r8(k0e(k0e1?"` J  sBeq(x$$`` 4   `|8(k(k 1?"`gY  Q0x$$`` 4   `D9(k(k 1?"`g  Q0x$$`` 4   ` 9(k(k 1?"`  Q0x$$`` 4   `9(k(k 1?"`J   Q0x$$``  4   `9(k(k 1?"`&G  w1=Immx$$``  4   `%9(k(k 1?"`J&  V0=zerox$$``  4   `\.9(k(k 1?"`J  Q1x$$``  4   `h89(k(k 1?"`  x0 = Rtx$$``  4   `A9(k(k 1?"`'  rxorix$$`` 4   `XJ9(k(k 1?"`J &  Qxx$$`` 4   `S9(k(k 1?"`J &  Qxx$$`` 4   ``\9(k(k 1?"`JI &  Qxx$$`` 4   `e9(k(k 1?"`Jv &I  V1=signx$$`` 4   `n9(k(k 1?"`J &v  V1=signx$$`` 4   ``9(k(k 1?"`J& V0=zerox$$`` 4   `p9(k(k 1?"`J*& V0=zerox$$`` 4   `09(k(k 1?"`JW&* V1=signx$$`` 4   `{9(k(k 1?"`J&W V1=signx$$`` 4   `ț9(k(k 1?"`J& Qxx$$`` 4  3 rȞ9(k0e(k0e1?"`J & \Ext Op(x$$`` 4   `Ю9(k(k 1?"`g Y  Qxx$$`` 4   `\9(k(k 1?"` g  Q0x$$`` 4   `P9(k(k 1?"`   Q0x$$`` 4   `9(k(k 1?"`J   Q0x$$`` 4   `9(k(k 1?"`& G  Qxx$$``  4   `\9(k(k 1?"` J  Q0x$$`` !4   `P9(k(k 1?"`   Qxx$$`` "4   `9(k(k 1?"`'   Ujx$$`` %4   `9(k(k 1?"`g Y  Qxx$$`` &4   `:(k(k 1?"` g  Q0x$$`` '4   `H :(k(k 1?"`   Q0x$$`` (4   `(:(k(k 1?"`J    Q1x$$`` )4   `:(k(k 1?"`& G  x0=BusBx$$`` *4   `T!:(k(k 1?"` J  Q0x$$`` +4   `t*:(k(k 1?"`   Qxx$$`` ,4   `::(k(k 1?"`'   qbnex$$`` -4   `C:(k(k 1?"`gI Y  Qxx$$`` .4   `L:(k(k 1?"`gv YI  Qxx$$`` /4   `G:(k(k 1?"`g Yv  Q1x$$`` 04   `_:(k(k 1?"`gY Q0x$$`` 14   `h:(k(k 1?"`g*Y Q0x$$`` 24   `p:(k(k 1?"`gWY* Q0x$$`` 34   `ly:(k(k 1?"`gYW Q0x$$`` 44   `,:(k(k 1?"`gY Q0x$$``C 54  3 rpt:(k0e(k0e1?"`g Y  Mem toReg ( $x$$`` ?4   `:(k(k 1?"`&I G   x0=BusBx$$`` @4   `ܟ:(k(k 1?"`&v G I  w1=Immx$$`` A4   `:(k(k 1?"`& G v  w1=Immx$$`` B4   `|:(k(k 1?"`&G  w1=Immx$$`` C4   `:(k(k 1?"`&*G  w1=Immx$$`` D4   `x:(k(k 1?"`&WG * w1=Immx$$`` E4   `:(k(k 1?"`&G W w1=Immx$$`` F4   `:(k(k 1?"`&G  x0=BusBx$$``7 G4  3 r:(k0e(k0e1?"`& G  ALU Src(x$$`` H4   `:(k(k 1?"`I J  Q0x$$`` I4   `:(k(k 1?"`v JI  Q0x$$`` J4   `D;(k(k 1?"` Jv  Q1x$$`` K4   ` ;(k(k 1?"`J Q1x$$`` L4   ` ;(k(k 1?"`*J Q1x$$`` M4   `H;(k(k 1?"`WJ* Q1x$$`` N4   `(%;(k(k 1?"`JW Q1x$$`` O4   `-;(k(k 1?"`J Q1x$$``1 P4  3 r0;(k0e(k0e1?"` J y Reg Write ( x$$``1 R4  3 rhA;(k0e(k0e1?"` g y Mem Write ( x$$``0 S4  3 rJ;(k0e(k0e1?"`  xMem Read ( x$$``+ T4  3 rlT;(k0e(k0e1?"`J  sBne(x$$``A U4  3 rh^;(k0e(k0e1?"`  Reg Dst($x$$`` V4  3 rg;(k0e(k0e1?'  XOp(x$$`` X4   `j;(k(k 1?"`Wg* Q0x$$`` Y4   `xy;(k(k 1?"`W* Q0x$$`` Z4   `;(k(k 1?"`J W* Q0x$$`` [4   `;(k(k 1?"`W* x0 = Rtx$$`` \4   `ܕ;(k(k 1?"`'W* rsltix$$`` ^4   `0;(k(k 1?"`g Q0x$$`` _4   `\;(k(k 1?"` Q0x$$`` `4   `;(k(k 1?"`J  Q0x$$`` a4   `L;(k(k 1?"` x0 = Rtx$$`` b4   `;(k(k 1?"`' qorix$$`` d4   `;(k(k 1?"`gW Q0x$$`` e4   `;(k(k 1?"`W Q0x$$`` f4   `<;(k(k 1?"`J W Q0x$$`` g4   `x;(k(k1?W x0 = Rtx$$``  h4   `@;(k(k1?'W raddix$$`` j4   `;(k(k1?I g  Q0x$$`` k4   `<(k(k1?I   Q0x$$`` l4   ` <(k(k1?J I   Q0x$$`` m4   `<(k(k1?I   Qxx$$``  n4   ` !<(k(k1?'I   qbeqx$$`` p4   `)<(k(k1?v gI  Q1x$$`` q4   `2<(k(k1?v I  Q0x$$`` r4   `;<(k(k1?J v I  Q0x$$`` s4   `D<(k(k1?v I  Qxx$$`` t4   `tN<(k(k1?'v I  pswx$$`` v4   `,W<(k(k1? gv  Q0x$$`` w4   ``<(k(k1? v  Q1x$$`` x4   `0R<(k(k1?J v  Q0x$$`` y4   `s<(k(k1? v  x0 = Rtx$$`` z4   `v<(k(k1?' v  plwx$$`` {4   `T<(k(k1?* Q0x$$`` |4   `<(k(k1? Q0x$$`` }4   `<(k(k1?* x0 = Rtx$$`` ~4   `\<(k(k1? V1 = Rdx$$`` 4   `ث<(k(k1?*g Q0x$$`` 4   `<(k(k1?g Q0x$$`` 4   `<(k(k1?J * Q0x$$``  4   `H<(k(k1?'* randix$$`` 4   `<(k(k1?J  Q0x$$`` 4   `@<(k(k1?' ZR-typex$$``xB 4  H 1 ?' Y rB 4  B 1 ?'YxB 4  H 1 ?' Y xB 4  H 1 ?' ' xB 4  H 1 ?Y Y rB 4  B 1 ? rB 4  B 1 ? rB 4  B 1 ? rB 4  B 1 ? rB 4  B 1 ?g grB 4  B 1 ?'YrB 4  B 1 ?'v Yv rB 4  B 1 ?'I YI rB 4  B 1 ?'WYWrB 4  B 1 ?'YrB 4  B 1 ?'*Y*rB 4  B 1 ? rB 4  B 1 ? rB 4  B 1 ? rB 4  B 1 ? rB 4  B 1 ?gg xB 4  H 1 ?'YrB 4  B 1 ?J JrB 4  B 1 ?JJ rB 4  B 1 ?G G rB 4  B 1 ?G G rB 4  B 1 ?' Y rB 4  B 1 ?' Y rB 4  B 1 ?& &rB 4  B 1 ?&& rB 4  B 1 ?' Y ZB 4  s *1 ?J J ZB 4  s *1 ?J J ZB 4  s *1 ?  ZB 4  s *1 ?  ZB 4  s *1 ? ZB 4  s *1 ? d 4 <1?|~ 4 s *T< `  <  4  f,<gֳgֳ ? `c < H 4 0޽h ? U>=UU(y___PPT10Y+D=' \= @B +5-  0 L,D,`":G8 0 +(  8  8  B< ="`  m = 4 X:8~ 8 s * = `  = vB 8 N DjJ? vB 8 N DjJ?P PvB 8 N DjJ? (8  M  G8 M,, B  8 B Z D1?  B  8  Z D1?  B  8 B Z D1?P P B  8  Z D1?  B  8 B Z D1?  B 8  Z D1?, , B 8  Z D1?  B 8 B Z Do?t t " 8   f Gv 1? P- B 8  Z Do?78 8   `\Z1?"`-M SOp640( 2 T p ;8 # t:B 8  Z D1?OOp 8  # lp=1?S"`?i LR-type*0 2  $T p <8 # :fB 8  Z D1?p. 8  # l=1?S"`?i daddi*0 2  $T Xp =8 # :B 8  Z D1?##p. 8  # l@=1?S"`?iX dslti*0 2  $T Xp >8 # :}B 8  Z D1?p. 8  # l=1?S"`?Xi dandi*0 2  #T ,p ?8 # :B 8  Z D1?p-  8  # l%=1?S"`?i, cori*0 2  $T ,p @8 # $:B !8  Z D1?aap. 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SADDx$$`` T<  # l|mA(kpG(kpG1?   plwx$$`` U<  # l+B#style.visibility<*x< %(D' =-o6Bdissolve*<3<*x< D' =%(D' =%(D@' =A@BB BB0B%(D' =1:Bvisible*o3>+B#style.visibility<*w< %(D' =-o6Bdissolve*<3<*w< +8+0+w< 0 +   0L0 # <(   ~  s * 7A `  A ~  s *7A ` A H  0޽h ? X(=^___PPT10i.D`+D=' \= @B +  0  @$" (   B  Z D1?@Y~  s *A `  A ~  s *,A'gm A   ZAjJ?"`@2  KInstruction Fetch0   ZlA1?"`6  ;Store0   ZhAfjJ?"`   =ALU0   ZAjJ?"`|  F Memory Write 0    ZAjJ?"`l@25 KInstruction Fetch0   ZA1?"`V66; 9ALU0   ZAfjJ?"`l2 5 ] Reg Read  0    ZAfjJ?"`l 5 =ALU0   ZlAjJ?"`R =/  KInstruction Fetch0   ZA1?"`: 6E  <Branch0   ZA1?"`6 :Load0   ZAjJ?"`3| E Memory Read 0    ZAjJ?"`2?1 KInstruction Fetch0   ZA1?"`|  I longest delay 0   ZAfjJ?"`2  =ALU0   ZAfjJ?"`22  ] Reg Read  0    ZCfjJ?"`4  ] Reg Read  0    ZCfjJ?"`R 0   ] Reg Read  0    ZL CfjJ?"`S   =ALU0   Z CjJ?"` =/  KInstruction Fetch0   ZdC1?"` 6E  :Jump0   Z8CfjJ?"` 0  BDecode  0   ! ZPCfjJ?"`lO5 ^ Reg Write  0   " Z CfjJ?"`2L ^ Reg Write  0  H  0޽h ? a(___PPT10i.\b;+D=' \= @B +!  0 80P$/ (      BD&C"` `  C ~  s *'C `  C ^l G\ g /  #"uq Gg   T3C1?g Q2x$$``   TL  B 1 ?X X =rB ?L  B 1 ?=rB @L  B 1 ?AA=rB AL  B 1 ? =`=xB BL  H 1 ? ` CL T8Eֳֳ ?"`'Yp,$@ 0 zFor fixed single-cycle implementation: Clock cycle = For multi-cycle implementation: Clock cycle = Average CPI = Speedup =t' < < < < <'  RB EL @ s *D  FL BEE"`0 zC Ddecode and update PC 2 GL BJE"  ,$  0 >*0.44 + 0.25 + 0.14+ 0.23 + 0.12 = 3.8 HL BNE a ,$ 0 n8max (200, 150, 180) = 200 ps (maximum delay at any step) IL B|SE a ,$ 0 k5880 ps determined by longest delay (load instruction)0J KL HVE"`H ,,$  0 *880 ps / (3.8 200 ps) = 880 / 760 = 1.16++B,H L 0޽h ? a(<4___PPT10.Zv+fD' Z= @B D' = @BA?%,( < +O%,( < +D' =%(D' =%(D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<*CL '%(D' =-o6Bdissolve*<3<*CL 'D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<*CL '5%(D' =-o6Bdissolve*<3<*CL '5D' =%(D' =%(D@' =A@BB BB0B%(D' =1:Bvisible*o3>+B#style.visibility<*IL %(D' =-o6Bdissolve*<3<*IL D' =%(D' =%(D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<*CL 5U%(D' =-o6Bdissolve*<3<*CL 5UD3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<*CL Uc%(D' =-o6Bdissolve*<3<*CL UcD' =%(D' =%(D@' =A@BB BB0B%(D' =1:Bvisible*o3>+B#style.visibility<*HL %(D' =-o6Bdissolve*<3<*HL D' =%(D' =%(D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<*CL cq%(D' =-o6Bdissolve*<3<*CL cqD' =%(D' =%(D@' =A@BB BB0B%(D' =1:Bvisible*o3>+B#style.visibility<*GL %(D' =-o6Bdissolve*<3<*GL D' =%(D' =%(D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<*CL q{%(D' =-o6Bdissolve*<3<*CL q{D' =%(D' =%(D@' =A@BB BB0B%(D' =1:Bvisible*o3>+B#style.visibility<*KL %(D' =-o6Bdissolve*<3<*KL ++0+GL 0 ++0+HL 0 ++0+IL 0 ++0+KL 0 +p  0 WW"LL@ GW(  @  @  B$)E"` `  E   `P @ # `,$D 0 N `P @  `PZB @ B s *1?TTB @  T D1?` @  0e0e    BzCDEF$ jJ 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E|| D=wz@PJ @   0e0e    BzCDEF$ jJ 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E|| D=wz@PJ  @  ZE1?"`w: <New PC B   @  ZE1?"`m: <Old PC B ZB  @  s *1?TT  @  ZE1?"`v \Clk-to-q  F   JP  @ # J,$D 0 @  0e0e    BzCDEF jJ 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||0jz @P @   0e0e    BzCDEF jJ 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||0jz @P`B @  01?#B @  T D1?#J# @  ZE1?"`#f XInstruction Memory Access Time F  @  Z`E1?"`0p EOld Instruction B Y @   `ЏE1?"`z0 7New Instruction = (Op, Rs, Rt, Rd, Funct, Imm16, Imm26)8 8B >  P  @ #  ,$D 0 @  0e0e    BzCDEF jJ 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||7pz @mPB @  T D1?* *  @   0e0e    BzCDEF jJ 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||7pz @mP @  ZE1?"`F m UDelay Through Control Logic F `B @  01?#*  @  ZlE1?"` OOld Control Signal Values B  @  ZE1?"`F  fNew Control Signal Values (ExtOp, ALUSrc, ALUOp, & )4 4B >  Pz  @ # z ,$D 0`B @  01?#p p N Pz  @  Pz   @  ZE1?"`  SRegister File Access Time F B !@  T D1?  z  "@   0e0e    BzCDEF jJ 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E|| z @PV  #@  0e0e    BzCDEF jJ 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E|| z @PV  $@  ZE1?"`9  fOld BusA Value B - %@   `ıE1?"` 9  New BusA Value = Register(Rs) B ,   W Pz  &@ # W z ,$D 0B '@  T D1?0 W 0 z  N s P  (@  s P `B )@  01?* 1  *@   0e0e    BzCDEF jJ 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||= w z @ P  +@  0e0e    BzCDEF jJ 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||= w z @ P , ,@   fE1?"`s  "Delay Through Extender and ALU Mux # #F  -@  Z0E1?"`=   JOld Second ALU Input B  .@   `E1?"`M =   _)New Second ALU Input = sign-extend(Imm16)* *B 1   P  /@ #   ,$D 0B 0@  T D1?s s `B 1@  01? # s#  2@  Z|E1?"`s Cz  C ALU Delay  F  3@   0e0e    BzCDEF jJ 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E|| z @z P  4@  0e0e    BzCDEF jJ 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E|| z @z P  5@  ZE1?"`   DOld ALU Result B  6@  ZE1?"`   NNew ALU Result = Address B    P 7@ #  ,$D 0B 8@  T D1?   N & Pc  9@  & Pc `B :@  01?s} }  ;@  ZE1?"`& :  SData Memory Access Time  F  <@   0e0e    BzCDEF jJ 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||Tz @ Pc  =@  0e0e    BzCDEF jJ 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||Tz @ Pc  >@   `E1?"` F  ROld Data Memory Output Value B  ?@  ZLE1?"`  jF  ? New Value  B { f Pf @@ #  f,$D  0l2 A@  <jJ? -`B B@  01?    C@  ZdE1?"`f f y#Mux delay + Setup time + Clock skew $ $F ! D@   `lE1?"` PJ H Write Occurs   F 0L `P0 E@ # `0}N `P0 F@  `P0B G@  T D1?`0  H@   0e0e    BzCDE F( jJ 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E|| z@`PB I@  T D1?`0 J@  ZE1?"`}m SClk B `B K@  01? L@  ZE1?"`f 60 G Clock Cycle   F H @ 0޽h ? a(___PPT10.Z`a5+,D^' Z= @B D' = @BA?%,( < +O%,( < +D' =%(D' =%(D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<*@ %(D' =-o6Bdissolve*<3<*@ D' =%(D' =%(D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<* @ %(D' =-o6Bdissolve*<3<* @ D' =%(D' =%(D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<*@ %(D' =-o6Bdissolve*<3<*@ D' =%(D' =%(D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<*@ %(D' =-o6Bdissolve*<3<*@ D' =%(D' =%(D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<*&@ %(D' =-o6Bdissolve*<3<*&@ D' =%(D' =%(D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<*/@ %(D' =-o6Bdissolve*<3<*/@ D' =%(D' =%(D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<*7@ %(D' =-o6Bdissolve*<3<*7@ D' =%(D' =%(D3' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<*@@ %(D' =-o6Bdissolve*<3<*@@ +  0 "D <(  D ~ D s *$G `  G ~ D s *G ` G H D 0޽h ? a(___PPT10i.eN0 W+D=' Z= @B +  0L0 "P <(  P ~ P s *G `  G ~ P s *G `x G H P 0޽h ? X(=^___PPT10i.a+D=' Z= @B + 0 4, (      `p~~1 ? P^L   lXThis slide shows how the next two lectures fit into the overall performance picture. Recalled from one of your earlier lectures that the performance of a machine is determined by 3 factors: (a) Instruction count, (b) Clock cycle time, and (c) Clock cycles per instruction. Instruction count is controlled by the Instruction Set Architecture and the compiler design so the computer engineer has very little control over it (Instruction Count). What you as a computer engineer can control, while you are designing a processor, are the Clock Cycle Time and Instruction Count per cycle. More specifically, in the next two lectures, you will be designing a single cycle processor which by definition takes one clock cycle to execute every instruction. The disadvantage of this single cycle processor design is that it has a long cycle time. +2 = 7 min. (X:47)p   01 ?|   H  0rllC ? X(=^80___PPT10.y`f 0  v(      ` ~~1 ? P^L    p   01 ?|   H  0rllC ? X(=^80___PPT10.P9`f 0   v(      `~~1 ? P^K    p   01 ?{   H  0rllC ? X(=^80___PPT10.zP.& 0 0  6(       `5~~1 ? P^L    In today s lecture, I will show you how to implement the following subset of MIPS instructions: add, subtract, or immediate, load, store, branch, and the jump instruction. The Add and Subtract instructions use the R format. The Op together with the Func fields together specified all the different kinds of add and subtract instructions. Rs and Rt specifies the source registers. And the Rd field specifies the destination register. The Or immediate instruction uses the I format. It only uses one source register, Rs. The other operand comes from the immediate field. The Rt field is used to specified the destination register. (Note that dest is the Rt field!) Both the load and store instructions use the I format and both add the Rs and the immediate filed together to from the memory address. The difference is that the load instruction will load the data from memory into Rt while the store instruction will store the data in Rt into the memory. The branch on equal instruction also uses the I format. Here Rs and Rt are used to specified the registers we need to compare. If these two registers are equal, we will branch to a location offset by the immediate field. Finally, the jump instruction uses the J format and always causes the program to jump to a memory location specified in the address field. I know I went over this rather quickly and you may have missed something. But don t worry, this is just an overview. You will keep seeing these (point to the format) all day today. +3 = 13 min. (X:53)U9AP4Pp   01 ?|   H  0rllC ? X(=^80___PPT10.pD`, 0 p  |(   d  c $wQ     3 rVkk T$K    H  0rllC ? a( 0   -(   }  S ~D=hmhm1 ? Q^M   As far as storage elements are concerned, we will need a N-bit register that is similar to the D flip-flop I showed you in class. The significant difference here is that the register will have a Write Enable input. That is the content of the register will NOT be updated if Write Enable is not asserted (0). The content is updated at the clock tick ONLY if the Write Enable signal is asserted (1). +1 = 31 min. (Y:11)p   01 ?|   H  0rllC ? X(=^  0   ! T (     S ~jhmhm1 ? Q^M   We will also need a register file that consists of 32 32-bit registers with two output busses (busA and busB) and one input bus. The register specifiers Ra and Rb select the registers to put on busA and busB respectively. When Write Enable is 1, the register specifier Rw selects the register to be written via busW. In our simplified version of the register file, the write operation will occurs at the clock tick. Keep in mind that the clock input is a factor ONLY during the write operation. During read operation, the register file behaves as a combinational logic block. That is if you put a valid value on Ra, then bus A will become valid after the register file s access time. Similarly if you put a valid value on Rb, bus B will become valid after the register file s access time. In both cases (Ra and Rb), the clock input is not a factor. +2 = 33 min. (Y:13)_!4 '1kR9p   01 ?|   H  0rllC ? X(=^v 0 6.0! (     S ~hmhm1 ? Q^M   PThe last storage element you will need for the datapath is the idealized memory to store your data and instructions. This idealized memory block has just one input bus (DataIn) and one output bus (DataOut). When Write Enable is 0, the address selects the memory word to put on the Data Out bus. When Write Enable is 1, the address selects the memory word to be written via the DataIn bus at the next clock tick. Once again, the clock input is a factor ONLY during the write operation. During read operation, it behaves as a combinational logic block. That is if you put a valid value on the address lines, the output bus DataOut will become valid after the access time of the memory. +2 = 35 min. (Y:15)t. rSMp   01 ?|   H  0rllC ? X(=^f 0 P! v(      `~~1 ? P^L    p   01 ?|   H  0rllC ? X(=^80___PPT10.`, 0 @"0 |(  0 d 0 c $wQ    0 3 rpjjjj U#K    H 0 0rllC ? a( 0 @8# (       `~~1 ? P^L   x0Here is an outline of today  s lecture. Mainly, we will be building a datapath step by step for a subset of the MIPS instruction set. +1 = 4 min. (X:44),(Kp   01 ?|   H  0rllC ? X(=^80___PPT10.F` 0 @8# (       `0~~1 ? P^L   x0Here is an outline of today  s lecture. Mainly, we will be building a datapath step by step for a subset of the MIPS instruction set. +1 = 4 min. (X:44),(Kp   01 ?|   H  0rllC ? X(=^80___PPT10.F` 0 @8# (       `蹀~~1 ? P^L   x0Here is an outline of today  s lecture. Mainly, we will be building a datapath step by step for a subset of the MIPS instruction set. +1 = 4 min. (X:44),(Kp   01 ?|   H  0rllC ? X(=^80___PPT10.F` 0 @8$ (       `À~~1 ? P^L   x0Here is an outline of today  s lecture. Mainly, we will be building a datapath step by step for a subset of the MIPS instruction set. +1 = 4 min. (X:44),(Kp   01 ?|   H  0rllC ? X(=^80___PPT10.F` 0 @80$ (       `X̀~~1 ? P^L   x0Here is an outline of today  s lecture. Mainly, we will be building a datapath step by step for a subset of the MIPS instruction set. +1 = 4 min. (X:44),(Kp   01 ?|   H  0rllC ? X(=^80___PPT10.F`rT z @ƧPS~!t Sg&Tlw?Q0;Kd͛ 6c  < j ls 5  |  C  M  f r  ^ 'Tp!z$ & l# Z! "% ( , V%5@ Nٓz0 81Oh+'0` `h     Single Cycle Processor DesignDr. Muhamed MudawarMuhamed Mudawar690Microsoft Office PowerPoint@7 @ И@OvG8g  L  y--$xx--'--$<<--'@BComic Sans MS-. 32 * Single Cycle Processor Designn."System8-@Arial-. 2 GBCOE 308.-@Arial-. '2 P2Computer Architecture.-@Arial-. '2 Z.Prof. Muhamed Mudawar.-@Arial-. 62 f'Computer Engineering Department.-@Arial-. L2 o.King Fahd University of Petroleum and Minerals.-՜.+,0     On-screen ShowKFUPM1 3 ;ArialComic Sans MS WingdingsTimes New Roman Courier NewSymbolDefault DesignSingle Cycle Processor DesignPresentation OutlineThe Performance Perspective$Designing a Processor: Step-by-Step#Review of MIPS Instruction FormatsMIPS Subset of InstructionsDetails of the MIPS SubsetRegister Transfer Level (RTL)#Instructions are Executed in StepsInstruction Execution contd$Requirements of the Instruction Set Next . . .Components of the DatapathRegister ElementMIPS Register FileDetails of the Register FileTri-State BuffersBuilding a Multifunction ALUInstruction and Data MemoriesClocking MethodologyDetermining the Clock Cycle Clock Skew Next . . .Instruction Fetching Datapath!Datapath for R-type Instructions%Datapath for I-type ALU Instructions$Combining R-type & I-type DatapathsControlling ALU InstructionsDetails of the ExtenderAdding Data Memory to Datapath"Controlling the Execution of Load#Controlling the Execution of Store#Adding Jump and Branch to DatapathDetails of Next PC"Controlling the Execution of Jump$Controlling the Execution of Branch Next . . .Main Control and ALU Control Single-Cycle Datapath + ControlMain Control SignalsMain Control Signal Values$Logic Equations for Control SignalsALU Control Truth Table Next . . .$Drawbacks of Single Cycle ProcessorMulticycle ImplementationPerformance Example Solution%Worst Case Timing (Load Instruction)Worst Case Timing Cont'dSummaryShl  Fonts UsedDesign Template Slide Titles3 Custom Shows'_1 0Muhamed MudawarMuhamed Mudawar  !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~      !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~      !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~      !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~      !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~      !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~      !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~Root EntrydO)Current UserSummaryInformation(PowerPoint Document(1 DocumentSummaryInformation8