MS THESES/PhD DISSERTATIONS SUPERVISED
PHD THESIS |
|||||
No. |
Candidate's NAME |
THESIS Title |
DEPT |
COMMITTEE |
DATE |
01 | Al-Somani, Turki Faisal |
Design and analysis of efficient and
secure elliptic curve cryptoprocessors. (Abstract/Full Text PDF) |
CSE |
Co-Advisor |
May 2006 |
02 | Al-Ghonaim, Esa |
Parallel computing simulation platform for
evaluating LDPC codes performance (Abstract/Full Text PDF) |
CSE |
Co-Advisor |
Dec 2008 |
MS THESIS |
|||||
No. |
Candidate's NAME |
THESIS Title |
DEPT |
COMMITTEE |
DATE |
01 | Hasan, Masudul |
Back-end design of a formal high level
synthesis system. (Abstract/Full Text PDF) |
COE |
Advisor |
Jun 1993 |
02 | Al-Mulhem, Abdulaziz Sultan | Hardware specific optimization on RTL description. (Abstract/Full Text PDF) |
COE |
Advisor |
Jun 1994 |
03 | Nassar, Khaled Muhammad Walid |
Timing driven placement algorithm for
standard-cell design. (Abstract/Full Text PDF) |
COE |
Advisor |
Jun 1994 |
04 | Khalid, Mohammed Abdul Aziz |
A framework for the VLSI
implementation of systolic tree based data structures. (Abstract/Full Text PDF) |
COE |
Advisor |
Sep 1994 |
05 | Hubbi, Essam Mohammad Khair |
Intermediate forms in high-level
synthesis. (Abstract/Full Text PDF) |
COE |
Advisor |
Nov 1994 |
06 | Khan, Mohammed Shahid Tanvir |
Genetic algorithm for timing
influenced floorplanning of VLSI designs. (Abstract/Full Text PDF) |
COE |
Advisor |
Dec 1994 |
07 | Abu-Saleh, Hazem Muhebbadin Ahmad Naji |
AutoVLSI system: a layout system for
general-cell VLSI design. (Abstract/Full Text PDF) |
COE |
Advisor |
Feb 1995 |
08 | Soleja, Faisal Mohammad Zafar |
Automated VHDL composition from AHPL.
(Abstract/Full Text PDF) |
COE |
Advisor |
Aug 1996 |
09 | Zahra, Mounir M. |
Optimization of mixed CMOS/BiCMOS
circuits using tabu search. (Abstract/Full Text PDF) |
COE |
Advisor |
Jul 1998 |
10 | Hussain, Ali Syed |
Fuzzy simulated evolution algorithm
for VLSI cell placement. (Abstract/Full Text PDF) |
COE |
Advisor |
Dec 1998 |
11 | Al-Yamani, Ahmad Abdul-Jabbar |
A Parallel Tabu search algorithm for
VLSI standard cell placement. (Abstract/Full Text PDF) |
COE |
Advisor |
May 1999 |
12 | Siddiqui, Mohammed Ahsan |
Data flow graph allocation to array
processors using iterative heuristics. (Abstract/Full Text PDF) |
COE |
Advisor |
Aug 2000 |
13 | Minhas, Mahmood-ur-Rehman |
Iterative algorithms for timing and
low power driven VLSI standard-cell placement. (Abstract/Full Text PDF) |
COE |
Advisor |
Jun 2001 |
14 | Al-Abaji, Raslan Hashim |
Evolutionary techniques for
multi-objective VLSI netlist partitioning. (Abstract/Full Text PDF) |
COE |
Advisor |
Aug 2002 |
15 | Al-Saiari, Uthman Salem | Digital circuit design through simulated evolution. (Abstract/Full Text PDF) |
COE |
Advisor |
Nov 2003 |
16 | Sanaullah, Syed |
Parallelization of Iterative
Heuristics for Performance Driven Low Power VLSI Standard Cell
Placement using Tabu search. (Abstract/Full Text PDF) |
COE | Advisor | Nov 2003 |
17 | Khan, Khawar Saeed |
Parallelization of stochastic
evolution. (Abstract/Full Text PDF) |
COE |
Advisor |
May 2006 |
18 | Siddiqi, Umair Farooq |
Parallel algorithms for look-up table
(LUT) inverse halftoning. (Abstract/Full Text PDF) |
COE |
Advisor |
Sep 2007 |
19 | Asadullah, Syed |
Optimization of metrics in OSPF/IS-IS
routing using accelerated iterative heuristics. (Abstract/Full Text PDF) |
COE |
Advisor |
Dec 2007 |
20 | Yazdani, Jaweed | A software tool to generate PCB layout from RTL specifications using SSI/MSI components. (Abstract/Full Text PDF) | ICS |
Co-Advisor/ Member |
May 1988 |
21 | Damati, Ali Fiqhi |
A Systolic algorithm for VLSI design
of a viterbi decoder. (Abstract/Full Text PDF) |
EE |
Co-Advisor/ Member |
Jun 1988 |
22 | Al-Hamed, Abdulaziz Hamed |
Data protection in a distributed
computer environment. (Abstract/Full Text PDF) |
ICS |
Co-Advisor/ Member |
Jul 1989 |
23 | El-Nafaty, Usman Aliyu |
Methanol conversion to light olefins
over commercial zeolites. (Abstract/Full Text PDF) |
CHE |
Co-Advisor/ Member |
Oct 1990 |
24 | Al-Massarani, Adel Mohammed Adel |
Priority-based scheduling and
evaluation of precedence graphs with communication times. (Abstract/Full Text PDF) |
COE |
Co-Advisor/ Member |
Aug 1993 |
25 | Al-Sukhni, Hassan Fakhri |
A C-Based high level synthesis system.
(Abstract/Full Text PDF) |
COE |
Co-Advisor/ Member |
Jan 1994 |
26 | Ali, Syed Asaf Maruf |
Design and modeling of a real-time
RISC processor in VHDL. (Abstract/Full Text PDF) |
COE |
Co-Advisor/ Member |
Jun 1994 |
27 | Abdulla, Abdul Hai Mohammed |
Reliability of modular fault-tolerant
hypercube networks. (Abstract/Full Text PDF) |
COE |
Co-Advisor/ Member |
Jan 1995 |
28 | Abu-Mutlaq, Maher Hamdan Khalil |
Dataflow processor for back
propagation neural networks: architecture and performance
evaluation. (Abstract/Full Text PDF) |
COE |
Co-Advisor/ Member |
Feb 1995 |
29 | Farooqui, Aamir Alam |
Design, modeling, and VLSI
implementation of a RISC dataflow array processor. (Abstract/Full Text PDF) |
EE |
Co-Advisor/ Member |
May 1995 |
30 | Al-Farra, Khalid Jawdat Kamel |
Timing driven floorplanning. (Abstract/Full Text PDF) |
COE |
Co-Advisor/ Member |
Jun 1995 |
31 | Hasan, Muhammad Nayyar |
On the synthesis and optimization of
MVL functions. (Abstract/Full Text PDF) |
COE |
Co-Advisor/ Member |
Jun 1995 |
32 | Farook, Mohammad |
Component selection and pipelining
using stochastic evolution. (Abstract/Full Text PDF) |
ICS |
Co-Advisor/ Member |
Jun 1996 |
33 | Alsayed, Sabih Masarrat |
A new traffic control scheme for ATM
networks. (Abstract/Full Text PDF) |
COE |
Co-Advisor/ Member |
Jul 1996 |
34 | Khan, Adnan Ahmed |
Development of a congestion control
scheme for ATM networks. (Abstract/Full Text PDF) |
COE |
Co-Advisor/ Member |
Oct 1996 |
35 | Nadeem, Mohammad Mohsin |
Evolution based scheduling of
precedence computations with communication costs. (Abstract/Full Text PDF) |
COE |
Co-Advisor/ Member |
Dec 1996 |
36 | Adiche, Hakim Salah |
Fuzzy genetic algorithm for VLSI
floorplan design. (Abstract/Full Text PDF) |
COE |
Co-Advisor/ Member |
Nov 1997 |
37 | Al-Kharobi, Talal Mousa Mohammed. |
Fuzzy logic based FPGA routing. (Abstract/Full Text PDF) |
COE |
Co-Advisor/ Member |
Jun 1998 |
38 | Al-Marhoun, Taisir I. |
Testing and evaluation methodology of
ATM systems. (Abstract/Full Text PDF) |
COE |
Co-Advisor/ Member |
Aug 1998 |
39 | Baig, Mirza Naved Ali |
Task matching and scheduling in
heterogeneous computing environments using iterative heuristics.
(Abstract/Full Text PDF) |
COE |
Co-Advisor/ Member |
May 1999 |
40 | Khan, Salman Ahmad |
Topology design of enterprise
networks. (Abstract/Full Text PDF) |
COE |
Co-Advisor/ Member |
Dec 1999 |
41 | Barnawi, Abdulaziz Yagoub |
Multicast routing protocol with
partial flooding for ad hoc wireless networks. (Abstract/Full Text PDF) |
COE |
Co-Advisor/ Member |
Jun 2001 |
42 | Shazli, Syed Zafar |
Experimenting with evolutionary
meta-heuristics for state justification in sequential ATPG. (Abstract/Full Text PDF) |
COE |
Co-Advisor/ Member |
Jun 2001 |
43 | Tahir, Muhammad Atif |
QoS-driven multicast routing
algorithms. (Abstract/Full Text PDF) |
COE |
Co-Advisor/ Member |
Jul 2001 |
44 | Mohammed, Yassir Obeid |
Quality of service routing. (Abstract/Full Text PDF) |
COE |
Co-Advisor/ Member |
Aug 2001 |
45 | Zakir, Ahmer |
Topological optimization of computer
networks subject to reliability and fault tolerance. (Abstract/Full Text PDF) |
COE |
Co-Advisor/ Member |
Aug 2002 |
46 | Al-Suwaiyan, Ali Saleh Mohammed |
Efficient test relaxation techniques
for combinational logic circuits. (Abstract/Full Text PDF) |
COE |
Co-Advisor/ Member |
Oct 2002 |
47 | Ya'u Isa, Garba |
Memory performance evaluation of high
throughput servers. (Abstract/Full Text PDF) |
COE |
Co-Advisor/ Member |
Jun 2003 |
48 | Osais, Yahya Esmail |
Efficient static test compaction
algorithms for combinational circuits based on test relaxation. (Abstract/Full Text PDF) |
COE |
Co-Advisor/ Member |
Oct 2003 |
49 | Faheemuddin, Mohammed |
Parallelization
of Evolutionary Algorithms applied to Multi-Objective VLSI Standard
Cell Placement. (Abstract/Full Text PDF) |
COE |
Co-Advisor/ Member |
Nov 2003 |
50 | Sarif, Bambang Ali Basyah |
Modified ANT colony algorithm for
combinational logic circuits design. (Abstract/Full Text PDF) |
COE |
Co-Advisor/ Member |
Nov 2003 |
51 | Khursheed, Syed Saqib |
Test set compaction for sequential
circuits based on test relaxation. (Abstract/Full Text PDF) |
COE |
Co-Advisor/ Member |
Dec 2004 |
52 | Sami, Muhammad Rehan |
Content-aware congestion control over
MPLS networks for multimedia transmission. (Abstract/Full Text PDF) |
COE |
Co-Advisor/ Member |
Jan 2005 |
53 | Khan, Faisal Nawaz |
FSM state-assignment for area, power
and testability using non-deterministic evolutionary heuristics. (Abstract/Full Text PDF) |
COE |
Co-Advisor/ Member |
May 2005 |
54 | Abdul Subhan, Abdul-Majid |
Designing of cellular mobile networks
using modern heuristics. (Abstract/Full Text PDF) |
COE |
Co-Advisor/ Member |
Jun 2005 |
55 | Ba-Abbad, Emran A. |
Ant colony multi-optimization
algorithm for circuit bi-partitioning. (Abstract/Full Text PDF) |
COE |
Co-Advisor/ Member |
Jun 2005 |
56 | Mohiuddin, Mohammed Aijaz |
Optimizing weights for OSPF to improve
utilization using modern heuristics. (Abstract/Full Text PDF) |
COE |
Co-Advisor/ Member |
Sep 2005 |
57 | Baig, Meerja Humayun |
Evolutionary heuristic optimization
for digital curves and surfaces. (Abstract/Full Text PDF) |
ICS |
Co-Advisor/ Member |
Oct 2005 |
58 | Mohiuddin, Khaja Mohammed |
Simulation Study Using OPNET for a New
Class of Network for Real Time Applications. (Abstract/Full Text PDF) |
COE |
Co-Advisor/ Member |
Mar 2006 |
59 | Ali, Mustafa Imran |
An efficient relaxation-based test
width compression technique for multiple scan chain testing.
(Abstract/Full Text PDF) |
COE |
Co-Advisor/ Member |
Dec 2006 |
60 | Zaidi, Ali Mustafa |
A modular reconfigurable architecture
for assymmetric and symmetric-key cryptography. (Abstract/Full Text PDF) |
COE |
Co-Advisor/ Member |
Jan 2007 |
61 | Ali, Mansoor | MultiObjective Optimization for FSM Synthesis Using Modern Evolutionary Techniques | COE |
Co-Advisor/ Member |
IP |
62 | Khan, Farhan | Transistor-Level Defect-Tolerant Techniques for Reliable Design at the Nanoscale | COE |
Co-Advisor/ Member |
Jul 2009 |
63 | Anwar, Taha |
Optimization of OSPF Weight Settings
by using Iterative Heuristics for Day to Day Traffic Demand Patterns |
COE |
Co-Advisor/ Member |
Jul 2009 |
64 | Al-Masri, Ahmed |
Design for Defect Tolerant Reliable
Digital System at the NanoScale |
COE |
Co-Advisor/ Member |
Jun 2009 |
65 | Farooqi, Mohammed Moinuddin Rizwan | Adapting Tabu search to accommodate online demand variations in a data network | COE |
Co-Advisor/ Member |
May2010 |
66 | Al-Qahtani, Ayed | Faculty tolerance techniques for sequential circuits: a design level approach | COE |
Co-Advisor/ Member |
Jul 2010 |
67 | Shaheen, Abdul-Rahman Salah Mohammed | A Comparative analysis of intelligent techniques for detecting anomalous Internet traffic | COE |
Co-Advisor/ Member |
Oct 2010 |
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