Multiple Channels Image Brightening Circuits on FPGA

The purpose of this experiment is to test the ability of using multiple threads to send and receive to and from multiple channels on the FPGA simultaneously and measure the aggregated throughput. To test throughput in this experiment, a simple brightening channel/circuit was used. This brightening circuit (channel) is replicated six times on the FPGA, but with different brightening values starting at 20 and ending at 120. The design of brightening channel is shown in Figure 1. It consists of an input FIFO, a saturating adder, an output FIFO, and Finite State Machine (FSM) to control filling and emptying the FIFOs. The brightening channel was chosen such that it can process 1 flit (i.e. 128-bit) every cycle such that there will be no bottleneck in the user’s logic in the FPGA

Brightening Channel Design
Figure 1: Brightening Channel Design.

The original image (i.e. before brightening) is shown in Figure 2. The original image has dimensions of 6000x4000 and size of 24 MB. Using a higher resolution image will result in higher aggregated throughput. Figure 3 shows what portions of the image a specific channel is responsible for brightening in case of using 6 channels and the brightening value of each channel/portion. The whole image is divided into 6 equal parts, and each part is sent to its dedicated channel using separate sending and receiving servant threads. This experiment has been conducted on Intel ® (Altera ®) Arria 10 GX Development Board using PCIe Gen 3.0 in 4 lanes configuration. The highest aggregated throughput achieved was 927.5 MB/s and 909.3 MB/s for downstream and upstream, respectively.

Image Before Brightening
Figure 2: Image Before Brightening.
Image Portions, Channel Assignment, and Brightening Values
Figure 3: Image Portions, Channel Assignment, and Brightening Values.