COE203: Digital Design Lab - Spring 2008 (T072)

Place: 22-340A
Time: 2:10-5:10pm (Monday)

Announcements

• Check your marks here
• Office hours this week: Sun/Mon (1:00pm-3:30pm)

Description

Review of Digital Logic Design: Design of Combinational Circuits, and Design of Sequential Circuits. Logic implementation using discrete logic components [TTL, CMOS], and programmable logic devices. Introduction to Field Programmable Logic Arrays [FPGAs]. The basic design flow: design capture [schematic capture, HDL design entry, design verification and test, implementation [including some of its practical aspects], and debugging. Design of data path and control unit.

Grading

• Experiments (8): 65%
• Quizzes (3): 15%
• Project: 20%

Lab Materials

• Syllabus [pdf]
• Lab manual [pdf]
• Lab guide [pdf]

Lab Notes

• Introduction [pdf]
• Exp#1 [pdf]
• Exp#2 [pdf]
• Exp#3 [pdf]
• Exp#4 [pdf]
• Exp#5 [pdf]
• Exp#6 [pdf]
• Exp#7 [pdf]
• Exp#8 [pdf]
• Project [Option 1, Option 2]

Resources

• WinLogiLab
• Verilog Tutorial by Peter M. Nyasulu [pdf]
• Digilent Spartan-3 Board: User Manual [pdf] - Brochure [pdf]
• Xilinx Spartan-3 FPGA [pdf]
• ISE 7 Tutorial [pdf]
• Debounce Verilog Code [debounce.v]
• Counter Verilog Code [counter.v]
• Circuit to generate 1Hz Clock[doc]
• Seven Segment Display: Circuit Demo [pps] - Sample Project [zip]
• AT28C64 [ROM] [pdf]
• 7474 [D Flip-Flops] [pdf]