COE 203 Term 161
Syllabus
Lab Manual:
- Experiment 01. Logic Gates (PDF)
- Experiment 02. Integrated Circuits; Electrical Properties and Specifications (PDF)
- Experiment 03. Digital Circuit Prototyping Using FPGAs (PDF)
- Experiment 04. Hierarchical Design (PDF)
- Experiment 05. Combinational Logic Design (PDF)
- Experiment 06. Counters and Registers (PDF)
- Experiment 07. Multiplier Design (PDF)
- Experiment 08. Clock (PDF)
- Experiment 09. Building a Digital Timer (PDF)
- Experiment 10. Reaction Timer: Part 1. Generating Random Delay (PDF)
- Experiment 11. Reaction Timer: Part 2. Response Time (PDF)
- Experiment 12. Traffic Light (PDF)