Place: 22-340B
Time: 2:10-5:10pm
Section: 56 (Monday)
Section: 58 (Tuesday)
Week | Topic | Slides |
01 (Feb 28) | Combinational Logic Design Review | Introduction [pdf, odp] Combinational Review [pdf, odp] |
02 (Mar 07) | Sequential Logic Design Review | Sequential Review [pdf, odp] |
03 (Mar 14) | Design with Discrete components | Exp 1 [pdf, odp] |
04 (Mar 21) | Design with EEPROM | Exp 2 [pdf, odp] |
05 (Mar 28) | Introduction to FPGAs design flow | Exp 3 [pdf, odp] |
06 (Apr 04) | Schematic design entry | Exp 4 [pdf, odp] |
07 (Apr 11) | Introduction to hardware description languages | Exp 5 [pdf, odp] |
08 (Apr 18) | Register Transfer Level modeling using verilog | Exp 6 [pdf, odp] |
09 (Apr 25) | --- Midterm Vacation ---- | |
11 (May 02) | Sequential circuits using verilog | Exp 7 [pdf, odp] |
12 (May 09) | Data path and control unit | Exp 8 [pdf, odp] |
13 (May 16) | ||
14 (May 23) | Project | Slides [pdf, odp] Project [pdf, odp] |
15 (May 30) | ||
16 (Jun 06) |